Dual-Trip Point Data Slicer Using Delayed Reference Thresholds
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Solution Overview
Problem
Traditional data slicers face challenges with reduced accuracy in establishing reference voltages, leading to timing errors and bit errors due to slew-rate limitations and the need for DC extraction, which can require additional time and lengthen data messages.
Innovation Solution
A dual-trip point data slicer that generates a reference signal by delaying and level-shifting the input signal, allowing for dynamic threshold adjustment and reducing errors caused by slew-rate limitations without the need for DC extraction or additional preamble bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DC extraction is used to establish reference voltage, then the reference voltage can be determined from the input signal, but timing errors occur due to slew-rate limitations and reduced accuracy in establishing the reference voltage
Solution Approach 1:
The patent applies preliminary action by generating a delayed version of the input signal before it is used for comparison. This delayed signal serves as a reference that anticipates the timing requirements, allowing the slicer to make accurate decisions without waiting for DC extraction to complete. The delay is carefully controlled to compensate for propagation delays and slew-rate limitations, thereby eliminating timing errors while maintaining reference voltage accuracy.
Solution Approach 2:
The patent introduces an intermediary element - a delay circuit - that mediates between the input signal and the reference voltage generation. This intermediary delays the input signal by a controlled amount, creating a reference signal that is synchronized with the comparator's decision timing. This intermediary approach avoids the timing errors associated with direct DC extraction while maintaining accurate reference voltage establishment.
2Adaptability or versatility
If DC extraction is performed to determine reference signal, then the slicing threshold can be dynamically adjusted, but additional time is required and data messages are lengthened
Solution Approach 1:
The patent uses preliminary action by pre-delaying the input signal to create the reference signal. This allows dynamic threshold adjustment to be achieved without requiring DC extraction, thereby maintaining data transmission efficiency. The delayed signal is ready immediately for comparison, eliminating the time penalty associated with DC extraction while still providing adaptive thresholding based on the actual input signal characteristics.
Solution Approach 2:
The patent extracts only the necessary timing information from the input signal by delaying it, rather than performing full DC extraction. This selective extraction approach provides the dynamic threshold adjustment capability needed for adaptability while avoiding the time-consuming nature of complete DC extraction, thus maintaining productivity.
3Device complexity
If fixed DC voltage threshold is used, then the circuit is simple, but reduced accuracy in establishing the reference voltage occurs
Solution Approach 1:
The patent maintains circuit simplicity by using a passive delay circuit rather than complex DC extraction and processing logic. The preliminary delay of the input signal provides accurate reference voltage establishment dynamically adapted to the actual signal characteristics, achieving high measurement precision with minimal additional circuit complexity.
Solution Approach 2:
The patent creates a copied version of the input signal with a controlled time delay. This copy serves as the reference signal for comparison, providing accurate and adaptive thresholding without requiring complex circuitry. The copying approach with delay achieves reference voltage accuracy while keeping the device complexity low.
Data Source
AI summary
A circuit can be configured to operate as a dual-trip point data slicer for serial demodulation. The circuit can include an input port configured to receive an input signal. The circuit can further include a first output port electrically coupled to the input port by a first circuit path. The circuit can further include the first circuit path, which can be configured to provide the input signal from the input port to the first output port. The circuit can further include a second output port electrically coupled to the input port by a second circuit path that is parallel to the first circuit path. The circuit can further include the second circuit path, which can be configured to provide a reference signal to the second output port. The reference signal can be based on a delayed version of the input signal.