Dual-Use Scan Latch for Reduced Chip Area and Complexity

Solution Overview

Problem

The existing internal scan chain testing methods for combinational logic circuits in integrated circuits require additional chip space and increase the complexity of the circuit, leading to a higher likelihood of faults and reduced reliability due to the need for multiplexed flip-flops along each data line.

Innovation Solution

Adapting output storage latches to support both functional processing and scan chain testing, allowing for a dual-use approach that reduces the number of transistors and simplifies the circuit layout, thereby reducing the surface area requirements and complexity, and strategically placing scan chain test points throughout the circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiplexed flip-flops are used along each data line for scan chain testing, then scan chain testing capability is achieved, but chip space increases and circuit complexity increases

Engineering Contradiction:

Improvescan chain testing capabilityVSAvoidchip space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The output storage latch is designed to perform both functional processing and scan chain testing operations. By making the latch universal, the patent eliminates the need for separate multiplexed flip-flops dedicated solely to scan testing, thereby reducing chip space while maintaining full scan chain testing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functional data path and scan test path into a single integrated structure using the output storage latch. The latch serves as a shared resource for both normal circuit operation and scan chain testing, merging previously separate functions into one cohesive unit that reduces overall hardware requirements.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If multiplexed flip-flops are used along each data line for scan chain testing, then scan chain testing capability is achieved, but circuit complexity increases

Engineering Contradiction:

Improvescan chain testing capabilityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The output storage latch is designed to perform both functional processing and scan chain testing operations. By making the latch universal, the patent eliminates the need for separate multiplexed flip-flops dedicated solely to scan testing, thereby reducing chip space while maintaining full scan chain testing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functional data path and scan test path into a single integrated structure using the output storage latch. The latch serves as a shared resource for both normal circuit operation and scan chain testing, merging previously separate functions into one cohesive unit that reduces overall hardware requirements.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If additional scan chain test points are placed throughout the circuit, then test coverage is improved, but device complexity increases

Engineering Contradiction:

Improvetest coverageVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The output storage latch is designed to perform both functional processing and scan chain testing operations. By making the latch universal, the patent eliminates the need for separate multiplexed flip-flops dedicated solely to scan testing, thereby reducing chip space while maintaining full scan chain testing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8464113B1Scan architecture for full custom blocks with improved scan latch

Publication Date: 2013.06.11 MARVELL ASIA PTE LTD

AI summary

A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.