Dual-VCO PLL Architecture for Multi-Frequency Clock Output

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Solution Overview

Problem

Conventional wireless distribution systems (WDS) require multiple phase locked loops (PLLs) to support different clock frequencies, leading to increased costs and space consumption due to duplicative solutions, especially in power-saving and space-constrained environments.

Innovation Solution

A single PLL with two voltage-controlled oscillators (VCOs) is used, where only one VCO is active at a time, sharing a phase detector and loop filter to generate feedback signals for different frequencies, reducing component count and space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple PLLs are used to support different clock frequencies, then frequency versatility is improved, but device complexity and space consumption increase

Engineering Contradiction:

Improvefrequency support capabilityVSAvoidPLL component count

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a single PLL circuit that can operate at multiple clock frequencies (e.g., 122.88 MHz for CPRI and 156.25 MHz for Ethernet) by incorporating two VCOs that share common PLL components (phase detector, loop filter, divider). This multi-functional design allows one PLL to replace what would traditionally require two separate PLLs, thereby reducing device complexity while maintaining frequency versatility

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges two VCOs into a single PLL architecture where both VCOs share the phase detector, loop filter, and control logic. The VCOs are selectively enabled based on the desired output frequency, allowing the system to consolidate multiple frequency-generating functions into a unified circuit structure, thus reducing the overall number of PLL components needed

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If multiple PLLs are used to support different clock frequencies, then frequency versatility is improved, but space consumption increases

Engineering Contradiction:

Improvefrequency support capabilityVSAvoidPLL circuit area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The single PLL circuit is designed to provide multiple clock frequencies (122.88 MHz, 156.25 MHz, and other intermediate frequencies) through two VCOs that share common components. This universal design eliminates the need for separate PLL circuits for each frequency, thereby significantly reducing the PCB area and physical space required while maintaining the ability to support multiple frequencies

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

By combining two VCOs under a single PLL control structure with shared phase detector and loop filter, the patent reduces the total circuit area. The selective enabling mechanism allows the system to switch between frequencies without requiring parallel PLL circuits, thus optimizing space utilization in the receiver device

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If multiple PLLs are used to support different clock frequencies, then frequency versatility is improved, but power consumption increases

Engineering Contradiction:

Improvefrequency support capabilityVSAvoidPLL power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent implements selective enabling of VCOs based on the required clock frequency. Only the VCO needed for the current operating mode is activated, while the other VCO remains disabled. This periodic or conditional activation pattern reduces average power consumption compared to having multiple PLLs continuously operating, while still maintaining the capability to support different frequencies when needed

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for cost and space savings while maintaining the ability to support multiple frequencies, enhancing the efficiency and performance of wireless distribution systems.

Implementation Method 1

The first VCO is configured to receive the control signal and output a first one of the two feedback signals. The second VCO is configured to receive the control signal and output a second one of the two feedback signals.

Methodology Applied

Scientific EffectVoltage-controlled oscillation:

Implementation Method 2

The phase detector is configured to receive a reference input signal and one of two feedback signals. The phase detector is also configured to output a control signal.

Methodology Applied

Scientific EffectPhase detection:

Data Source

PatentUS10523222B1Systems and methods for using a phase locked loop (PLL) to provide multiple output signals

Publication Date: 2019.12.31 ANI ACQUISITION SUB LLC

AI summary

A phase locked loop (PLL) provides output signals at multiple frequencies. In particular, the PLL includes a phase detector and two voltage controlled oscillators (VCOs). One of the VCOs is selectively enabled depending on a desired output signal. The phase detector receives a reference signal and a feedback signal from the enabled one of the two VCOs. The phase detector outputs a control signal that controls the VCO that provided the feedback signal.