Dual Vertical Gate Transistor for Compact Memory
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Solution Overview
Problem
Resistive memory technologies face challenges in compactness due to the area occupied by selection transistors and the formation of parasitic conduction channels in vertical-gate configurations, which can cause errors during memory cell access, and require high current for writing data.
Innovation Solution
The method involves producing MOS transistors with two vertical gates, where two parallel trenches are etched in a semiconductor substrate, and gate material is deposited on the substrate and trenches, allowing for electrical connection between the gates, thereby isolating them and enabling increased current flow without covering the trench bottom, which minimizes area usage and prevents parasitic conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical-gate selection transistors are formed to reduce area, then compactness is improved, but parasitic conduction channels are formed causing errors
Solution Approach 1:
The patent divides the gate structure into two separate vertical gates instead of using a single gate or doping region. This segmentation allows each gate to be independently controlled and positioned, enabling effective isolation of adjacent transistors while maintaining compact area. The two gates are formed in parallel trenches with their respective active regions, creating a segmented architecture that prevents parasitic conduction channels.
2Reliability
If doping is applied to limit parasitic conduction, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for doping by replacing it with a purely geometric solution. Instead of modifying the electrical properties of regions through doping, the invention uses the physical arrangement and isolation of two vertical gates to prevent parasitic conduction. This extraction of the doping function simplifies the device structure while maintaining reliability.
3Power
If two vertical gates are formed with isolated regions, then current flow is doubled, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of two vertical gates into a unified manufacturing process sequence. Both gates are formed using the same trench etching, gate material deposition, and isolation steps, performed simultaneously or in close succession. This merging of operations into a standardized flow reduces manufacturing complexity despite the increased structural complexity of having two gates.
4Reliability
If vertical gates rest on trench bottom to enable isolation, then parasitic conduction is prevented, but area occupied increases
Solution Approach 1:
The patent transitions from planar isolation to vertical isolation by having gates rest on the trench bottom. This dimensional change allows isolation to be achieved in the vertical dimension rather than requiring lateral separation. The gates are positioned at the bottom of deep trenches, using the trench depth to provide isolation while minimizing the lateral footprint of the transistor structure.
Data Source
AI summary
A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.