Dual Volatile Cache Architecture for NAND Read Disturbance
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Solution Overview
Problem
Memory devices with non-volatile NAND memory suffer from read disturbance and cache trashing due to frequent replacement of data in volatile cache memory, leading to slowed response times and potential read errors, especially when multiple read requests access the same location.
Innovation Solution
A memory device with a control circuit, a first volatile cache memory for storing data to be written or read from non-volatile memory, and a second volatile cache memory dedicated for read operations, which uses a least-recently-used or frequency-based replacement policy to minimize cache trashing and read disturbance by storing additional pages in the second cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a small volatile cache memory is used to store frequently requested data, then cache access speed is improved, but cache trashing occurs when multiple frequently accessed pages map to the same cache line, causing data to be continually replaced and requiring direct NAND memory access
Solution Approach 1:
The cache memory is divided into two separate caches: a first volatile cache memory for write operations and a second volatile cache memory for read operations. This segmentation allows each cache to be optimized for its specific function, preventing cache trashing by dedicating the second cache solely to read requests, thereby maintaining high cache hit rates for read operations while preserving fast access speed.
2Productivity
If data is frequently read from the same location in NAND memory, then data retrieval is achieved, but read disturbance occurs over time causing read errors
Solution Approach 1:
The second volatile cache memory is used to pre-load and store pages of NAND memory that are likely to be read. When a read request occurs, the data is retrieved from the second cache memory rather than directly from NAND memory. This preliminary action of caching read data prevents excessive reading of the same NAND memory locations, thereby reducing read disturbance and read errors while maintaining efficient data retrieval.
3Productivity
If the cache memory is used to store entire pages from NAND memory, then efficient data retrieval is improved, but the cache memory size requirement increases
Solution Approach 1:
The cache system is segmented into two separate volatile cache memories, each handling specific operations (write and read). This segmentation allows the second cache to be optimized for read operations with appropriate sizing, while the first cache handles write operations. The division enables efficient page-level caching without requiring a single large cache, as each cache can be sized according to its specific operational requirements.
Data Source
AI summary
A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.