Dual Voltage CMOS Receiver Circuit Design
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Solution Overview
Problem
High-speed CMOS receiver circuits fabricated at 28 nm or lower scales face challenges in supporting higher voltage levels like 3.3V while maintaining power and area efficiency, as conventional designs compromise noise immunity and performance due to operational voltage stress.
Innovation Solution
A dual voltage range receiver circuit that generates reference bias voltages to control signal propagation through either an upper or lower range data path, using only 35 Å oxide devices, allowing for high switching speed and protection of sensitive circuitry by limiting voltage ranges to safe values, thereby enabling operation across 0-3.3V and 0-1.8V ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 35 Å oxide thickness devices are used to support 3.3V operation, then voltage compatibility is improved, but noise immunity and performance deteriorate due to operational voltage stress
Solution Approach 1:
The receiver circuit is divided into multiple stages: a clamp transistor stage (MN5) that segments the voltage range, a Schmitt trigger stage (MP1-MN1) for digitization, and a level shifter stage (MP2-MN2) for output conditioning. This segmentation allows the 35 Å oxide devices to handle 3.3V input signals by breaking down the voltage stress across multiple circuit stages, with the clamp transistor protecting subsequent stages from excessive voltage while maintaining noise immunity through proper threshold voltage design.
2Speed
If 35 Å oxide thickness devices are used for high speed operation, then switching speed is improved, but the circuit cannot sustain voltages beyond 2.0V
Solution Approach 1:
The clamp transistor MN5 acts as an intermediary element between the 3.3V input signal and the 35 Å oxide devices. It clamps the voltage to safe levels (1.8V - Vt) before the signal reaches the sensitive high-speed circuitry, allowing the fast 35 Å oxide devices to operate at full speed while the intermediary clamp transistor absorbs the voltage stress that these devices cannot tolerate.
3Adaptability or versatility
If a native NMOS transistor is used as clamp transistor to improve voltage handling, then voltage tolerance is improved, but device area increases by 2-3 times
Solution Approach 1:
Instead of changing the physical dimensions of the clamp transistor to improve voltage handling (which would increase area), the invention changes the operating parameters by using a standard-sized NMOS transistor with appropriate threshold voltage characteristics. The transistor is biased and configured to function as a voltage clamp, achieving voltage handling capability through parameter optimization rather than physical scaling, thus maintaining area efficiency while improving voltage tolerance.
Data Source
AI summary
An input signal is split onto a first data path and a second data path. Values of the input signal above a threshold voltage level are propagated on the second data path and not on the first data path. The propagation of the signal from the input signal terminal through the first data path or the second data path is selectively controlled using two reference bias voltages generated based on a level of the signal.