Dual-Voltage I/O Circuit Biasing Without Resistor Dividers
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Solution Overview
Problem
Existing dual voltage input-output circuits in battery-powered devices face challenges in conserving power and reducing silicon area due to the use of resistor-based voltage dividers, which consume static power and require significant space for fabrication.
Innovation Solution
A driver circuit with a p-channel FET and an n-channel FET, coupled with a predriver circuit and a bias circuit, generates a bias voltage by subtracting the system voltage from the peripheral voltage, eliminating the need for resistors and reducing static power consumption, while ensuring symmetrical rise and fall transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If resistor-based voltage dividers are used to generate bias voltages, then voltage level shifting is achieved, but static power consumption increases and silicon area increases
Solution Approach 1:
The patent extracts and removes the resistor-based voltage divider circuitry from the design, replacing it with a capacitor-based implementation. This extraction eliminates the static power consumption and silicon area occupied by resistors while maintaining the voltage level shifting function through capacitive coupling and switching mechanisms.
Solution Approach 2:
The patent substitutes the passive resistor-based voltage division mechanism with an active capacitor-based system controlled by switches. This replacement transforms the static resistive voltage divider into a dynamic capacitive voltage generator that can operate without continuous power consumption, thereby reducing both static power and silicon area requirements.
2Adaptability or versatility
If multiple level shifters are added to support increasing data bus widths and voltage domains, then compatibility across voltage levels is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal level shifter design that can operate across multiple voltage domains and data bus widths through configurable switching networks. The same basic circuit architecture can be adapted to different voltage levels (1.8V, 3.3V, 5V) and bus configurations, reducing the need for multiple specialized level shifters and thereby simplifying overall device complexity while maintaining broad compatibility.
Data Source
AI summary
In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage.


