Dual-Voltage Logic Cell Keeper Timing for Race-Free Memory Reads
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Solution Overview
Problem
Signal race conditions and timing issues arise in circuits with multiple voltage domains due to leakage and contention between keeper and pull-down devices, particularly in memory banks with hierarchical bitline structures, leading to inaccurate read operations.
Innovation Solution
Implementing a keeper circuit with adaptive timing adjustment based on supply voltage variations, using both read and write domain voltages to maintain the global read evaluation signal within a critical timing window, and modulating the keeper signal delay through a clock line with dual-domain biased transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a keeper circuit is used to retain the global bitline state, then the bitline state stability is improved, but timing accuracy deteriorates due to PVT variations and voltage domain differences
Solution Approach 1:
The keeper circuit's activation timing is made dynamic by using adaptive delay elements that adjust their delay based on supply voltage levels. The delay element has different delay characteristics when operated at read domain voltages versus write domain voltages, allowing the keeper to activate at the optimal moment regardless of voltage domain crossings, thus resolving the timing accuracy issue while maintaining state stability
Solution Approach 2:
The patent changes the operational parameters of the keeper circuit by enabling it to function across multiple voltage domains (read domain and write domain). The delay element's propagation delay is modified based on the supply voltage level, allowing the keeper circuit to adapt its timing behavior to different voltage conditions and maintain accurate read operations despite PVT variations
2Adaptability or versatility
If the keeper circuit operates across wide PVT variations, then the circuit's adaptability is improved, but current leakage increases causing contention with pull-down devices
Solution Approach 1:
The keeper circuit incorporates feedback mechanisms where the delay element's propagation delay is monitored and adjusted based on the supply voltage level. This feedback allows the keeper to automatically adjust its activation timing to compensate for voltage domain differences and PVT variations, reducing unwanted current leakage and contention while maintaining adaptability across wide operating conditions
3Adaptability or versatility
If dual-voltage operation is implemented for bitcells and read ports, then the circuit's versatility is improved, but signal race conditions increase due to different potential levels
Solution Approach 1:
The adaptive delay element acts as an intermediary between the bitcell output and the read port evaluation. It mediates the voltage domain crossing by adjusting its delay characteristics based on the supply voltage level, ensuring that signals are evaluated at the correct time regardless of whether the bitcell or read port is operating at a higher or lower potential, thus preventing signal race conditions while maintaining dual-voltage versatility
Data Source
AI summary
Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.