Dual Voltage Supply for Memory Burn-In Stress Testing
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Solution Overview
Problem
Existing memory systems face challenges in generating stress voltages for burn-in testing without degrading peripheral circuitry, as increasing the voltage supply for digit lines can lead to current leakage and circuitry degradation.
Innovation Solution
Utilizing a second voltage supply isolated from peripheral circuitry to generate stress voltages for digit lines during burn-in, while using a first voltage supply for non-burn-in modes, thereby preventing high voltage application to peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage supply for digit lines is increased to generate stress voltages for burn-in testing, then the burn-in testing capability is improved, but current leakage and peripheral circuitry degradation occur
Solution Approach 1:
The voltage supply system is segmented into two independent voltage supplies: a first voltage supply for non-burn-in modes and a second voltage supply for burn-in modes. This segmentation allows each voltage supply to be optimized for its specific function, enabling high voltage stress testing without exposing peripheral circuitry to harmful high voltage conditions.
Solution Approach 2:
The harmful high voltage stress is extracted and isolated to only the memory array portion during burn-in testing, while peripheral circuitry remains connected to the lower voltage first supply. This extraction eliminates the harmful interaction between high voltage stress and sensitive peripheral components.
2Device complexity
If a single voltage supply is used for both burn-in and non-burn-in modes, then device complexity is reduced, but peripheral circuitry degradation occurs during burn-in
Solution Approach 1:
The voltage supply system is divided into two independent supplies with distinct functions. The first voltage supply serves peripheral circuitry during all modes, while the second voltage supply provides high voltage stress only to the memory array during burn-in. This segmentation protects peripheral circuitry while enabling comprehensive burn-in testing.
Solution Approach 2:
The memory array acts as an intermediary that receives high voltage stress from the second supply during burn-in while isolating peripheral circuitry from this stress. The controlled coupling and decoupling mechanisms mediate between the high voltage source and sensitive components.
3Reliability
If high voltage is applied to digit lines during burn-in, then stress testing effectiveness is improved, but current leakage increases
Solution Approach 1:
The high voltage stress is extracted and confined exclusively to the memory array during burn-in testing. By decoupling peripheral circuitry from the high voltage supply, current leakage paths through peripheral components are eliminated while maintaining effective stress testing on the memory array.
Solution Approach 2:
High voltage stress is applied locally only to the memory array where it is needed for effective burn-in testing, while peripheral circuitry operates at normal lower voltages. This localized application of high voltage achieves stress testing goals without causing system-wide current leakage.
Data Source
AI summary
Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.