Dual-Voltage Memory Interface for Speed and Power Balance
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in increasing operating speed and reducing power consumption, as lower operating voltages for data receivers lead to decreased speed and insufficient power consumption reduction.
Innovation Solution
A memory device design where the data receiver and peripheral circuits are driven by different voltage values, with the data receiver operating at a higher voltage to enhance speed and the latch driver and voltage level shifter operating at lower voltages to reduce power consumption, allowing for efficient data transmission and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the data receiver is driven by a lower operating voltage to reduce power consumption, then power consumption is reduced, but the operating speed of the memory device decreases
Solution Approach 1:
The patent applies different voltage levels to different components within the memory device. Specifically, the data receiver operates at a first voltage level (e.g., 1.1V) to maintain high-speed data reception, while peripheral circuits operate at a second voltage level (e.g., 0.6V) to reduce power consumption. This local differentiation of operating conditions resolves the contradiction by allowing speed-critical components to run fast and power-critical components to run efficiently.
Solution Approach 2:
The memory device is segmented into distinct voltage domains: a first voltage domain for the data receiver and a second voltage domain for peripheral circuits. The voltage level shifter acts as an interface between these domains, enabling independent voltage optimization for each segment. This segmentation allows the system to achieve both high speed in the data receiver and low power consumption in peripheral circuits simultaneously.
2Speed
If all peripheral circuits are driven by higher operating voltages to maintain speed, then operating speed is maintained, but the effect of power consumption reduction becomes insignificant
Solution Approach 1:
Instead of uniformly driving all peripheral circuits at high voltage, the patent selectively applies high voltage only where necessary (data receiver) and low voltage where power savings are prioritized (peripheral circuits). This localized approach to voltage assignment maintains overall system speed while achieving significant power consumption reduction.
Solution Approach 2:
The patent changes the operating voltage parameter for different circuit blocks based on their functional requirements. The data receiver uses a higher voltage (first voltage) for high-speed operation, while peripheral circuits use a lower voltage (second voltage) for power efficiency. The voltage level shifter enables this parameter differentiation by translating signals between the two voltage domains.
Data Source
AI summary
A memory device includes a data receiver, a latch driver, and a voltage level shifter. The data receiver works in a first voltage, receives an enable signal, a reference signal, and an input data signal, and outputs an internal data signal by the first voltage. The latch driver receives a write select signal and the internal data signal, latches the internal data signal by the first voltage, and outputs at least one latch data signal by a second voltage. The voltage level shifter receives the at least one latch data signal by the second voltage and generates at least one output data signal by the at least one latch data signal. The voltage level shifter sets a voltage value of the at least one output data signal by the first voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage.