Dual-Voltage Memory I/O Using 3-Level PAM for Lower Power
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Solution Overview
Problem
Conventional memory systems face challenges in achieving high performance and low power consumption while supporting flexible memory package options and configurations, particularly in next-generation low-power double data rate (LPDDR) memory applications.
Innovation Solution
The implementation of a memory system using dual input/output (IO) voltage supplies with a 3 level pulse amplitude modulation (PAM) scheme, where a memory device and memory physical layer communicate using two dedicated or shared IO voltage supplies, allowing for increased bandwidth and reduced power consumption by utilizing a lower voltage supply in addition to a higher voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single high voltage IO supply is used to achieve high performance, then bandwidth and speed are improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage selection by providing two IO voltage supplies (first and second IO voltage supplies) that can be selectively activated based on operational requirements. The system dynamically switches between single-supply mode (high performance), dual-supply mode (balanced performance and power savings), and powered-down mode (minimal power consumption), allowing the memory device to adapt its power consumption and performance characteristics to match actual workload demands.
Solution Approach 2:
The patent changes the voltage parameter by introducing a second IO voltage supply with a different voltage level than the first IO voltage supply. The memory device can selectively connect to either the first IO voltage supply, the second IO voltage supply, or both simultaneously, thereby changing the operational voltage parameters to optimize the trade-off between performance and power consumption based on the specific operational context.
2Use of energy by moving object
If dual IO voltage supplies are used to reduce power consumption, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The patent enhances universality by making the second IO voltage supply shareable across multiple memory devices. The second IO voltage supply can be commonly shared among several memory devices in the system, allowing the complexity of providing a second voltage supply to be amortized across multiple devices. This multi-functionality approach enables power reduction benefits to be achieved while distributing the complexity burden across the entire memory subsystem rather than individual devices.
3Productivity
If 3 level PAM scheme is implemented to increase bandwidth, then data transmission efficiency is improved, but signaling complexity increases
Solution Approach 1:
The patent changes the signaling parameter by implementing a 3-level Pulse Amplitude Modulation (PAM) scheme that utilizes three distinct voltage levels: a first voltage level (e.g., ground or low voltage), a second voltage level (e.g., intermediate voltage), and a third voltage level (e.g., high voltage or rail voltage). This parameter change in the signaling scheme enables the transmission of more information per signal transition, thereby increasing data transmission bandwidth and productivity while managing the associated signaling complexity through systematic voltage level utilization.
Data Source
AI summary
Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.