Dual-Voltage Memory I/O Using 3-Level PAM for Low-Power Bandwidth
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Solution Overview
Problem
Conventional memory systems face challenges in achieving high performance and low power consumption while maintaining competitive costs and flexible configuration options, particularly in next-generation LPDDR memory applications.
Innovation Solution
Implementing a memory system with dual input/output (IO) voltage supplies that utilize a 3 level pulse amplitude modulation (PAM) IO scheme, where a memory device and physical layer communicate using two dedicated or shared IO voltage supplies, allowing for increased bandwidth and reduced power consumption by selectively connecting to different voltage levels or ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single IO voltage supply is used in conventional memory systems, then device complexity is reduced, but power consumption increases and bandwidth is limited
Solution Approach 1:
The IO voltage supply is segmented into multiple independent voltage supplies (first IO voltage supply and second IO voltage supply), each capable of operating at different voltage levels. This segmentation allows selective activation of voltage supplies based on performance requirements, reducing overall power consumption while maintaining the ability to achieve high bandwidth when needed.
Solution Approach 2:
The memory system dynamically selects between different IO voltage supplies and voltage levels based on operational requirements. The system can switch between low-voltage mode (lower power consumption) and high-voltage mode (higher bandwidth), providing adaptive power management that balances performance and energy efficiency in real-time operations.
2Productivity
If higher IO voltage levels are used to increase bandwidth, then data transmission speed improves, but power consumption increases
Solution Approach 1:
The system dynamically adjusts IO voltage levels based on bandwidth requirements. During high-performance operations, the system activates higher voltage supplies to increase data transmission speed. During normal operations, lower voltage supplies are used to reduce power consumption. This dynamic adaptation allows the system to optimize the trade-off between bandwidth and power consumption for different workloads.
Solution Approach 2:
The system changes the voltage parameter of the IO supplies based on operational needs. By providing multiple IO voltage supplies with different voltage levels, the system can adjust the voltage parameter to match the required performance level, achieving high bandwidth only when necessary and reducing power consumption during standard operations.
3Productivity
If dual IO voltage supplies are implemented, then power consumption is reduced and bandwidth is increased, but device complexity increases
Solution Approach 1:
The multiple IO voltage supplies are designed to be universally applicable across different operational modes and performance requirements. The same voltage supply architecture supports both low-power mode and high-bandwidth mode, as well as various intermediate performance levels. This multi-functionality reduces the need for separate specialized circuits for different operations, thereby limiting the increase in device complexity.
4Productivity
If 3 level PAM IO scheme is used, then data transmission efficiency improves, but signal integrity requirements increase
Solution Approach 1:
The system uses different voltage levels from the multiple IO voltage supplies to represent different signal states in the 3-level PAM scheme. By having precise control over voltage levels, the system can maintain distinct and well-defined signal states, improving signal integrity. The ability to select from multiple voltage supplies allows optimization of voltage margins and signal levels to accommodate the higher requirements of 3-level PAM transmission.
Data Source
AI summary
Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.