Dual-Voltage Memory I/O with 3-Level PAM for Power-Bandwidth Tradeoffs

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Solution Overview

Problem

Existing memory systems face challenges in achieving high performance and low power consumption while maintaining competitive memory costs and flexibility in package types and sourcing.

Innovation Solution

The implementation of a memory system using dual input/output (IO) voltage supplies, which includes a memory device and a memory physical layer communicating data through a 3 level pulse amplitude modulation (PAM) IO scheme, allowing for improved performance and reduced power demand.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional single IO voltage supply is used, then device complexity is reduced, but power consumption increases and bandwidth performance deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidvoltage supply structure

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The single IO voltage supply is segmented into two separate voltage supplies (first IO voltage supply and second IO voltage supply) with different voltage levels. This segmentation allows independent optimization of power consumption and performance by selectively using appropriate voltage levels for different operational modes, thereby reducing overall power consumption while maintaining system functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system changes the voltage parameter by introducing a second IO voltage supply with a different voltage level than the first IO voltage supply. This parameter change enables the memory device to operate in different power modes, selecting lower voltage for reduced power consumption scenarios and higher voltage for high-performance scenarios, thus resolving the contradiction between power consumption and performance.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If conventional single IO voltage supply is used, then device complexity is reduced, but bandwidth performance deteriorates

Engineering Contradiction:

Improvememory bandwidthVSAvoidvoltage supply structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The single IO voltage supply is segmented into two separate voltage supplies, enabling the system to selectively apply higher voltage levels during high-bandwidth operations. This segmentation provides the flexibility to optimize bandwidth performance when needed while avoiding the continuous power overhead of high-voltage operation, thus improving productivity without proportionally increasing complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between the first IO voltage supply and the second IO voltage supply based on operational requirements. This dynamic voltage selection allows the memory device to adapt its performance characteristics in real-time, achieving high bandwidth when required while maintaining lower power consumption during normal operations, thereby improving overall productivity.

Inventive Principle:

Principle #15Dynamics

3Power

If dual IO voltage supplies with 3 level PAM are implemented, then power consumption is reduced and bandwidth is enhanced, but device complexity increases

Engineering Contradiction:

Improvepower efficiencyVSAvoidvoltage supply and signaling structure

Core Design Contradiction:

PowerVSDevice complexity

Solution Approach 1:

The patent merges the dual IO voltage supply system with the 3-level PAM signaling scheme to achieve synergistic power and performance benefits. By combining these two features, the system encodes more data per signaling event (improving bandwidth efficiency) while using lower voltage levels more frequently (improving power efficiency), thereby achieving better overall power efficiency despite the increased complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The dual IO voltage supplies serve multiple functions: they provide different voltage levels for power optimization and enable the 3-level PAM signaling scheme for enhanced bandwidth. This multi-functionality justifies the increased complexity by delivering dual benefits in both power efficiency and data transmission capability from a single architectural enhancement.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Speed

If dual IO voltage supplies with 3 level PAM are implemented, then conventional performance limitations are overcome, but device complexity increases

Engineering Contradiction:

Improvedata transfer speedVSAvoidvoltage supply and signaling structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP4285202B1Low power memory system using dual input-output voltage supplies

Publication Date: 2025.06.11 QUALCOMM INC

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AI summary

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.