Dual-Voltage Memory Architecture for Stable Low-Power SoC Access
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Solution Overview
Problem
The increasing parasitic elements in integrated circuits due to reduced wiring widths and heights, along with lower power supply voltages, affect the stability and performance of memory devices, particularly in System-on-Chip applications, necessitating improved energy efficiency and performance.
Innovation Solution
A memory device design that utilizes dual supply voltages, where the cell array and associated circuits operate at a higher voltage for improved performance and reduced power consumption, while external circuits operate at a lower voltage, with a level shifter to convert signals between these voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to minimize energy consumption, then energy consumption is reduced, but the impact of parasitic elements increases and performance stability deteriorates
Solution Approach 1:
The memory device is divided into two voltage domains: a first voltage domain for the cell array and core memory circuits, and a second voltage domain for peripheral access circuits. This segmentation allows each domain to operate at its optimal voltage level, with the cell array running at higher voltage for stable performance and peripheral circuits at lower voltage for reduced power consumption.
Solution Approach 2:
Different parts of the memory device are assigned different voltage characteristics. The cell array and core circuits operate at a first supply voltage optimized for performance and stability, while peripheral circuits operate at a second supply voltage optimized for power consumption. This local quality differentiation resolves the contradiction between overall power reduction and local performance stability.
2Quantity of substance
If wiring width and height are reduced to increase integration density, then integration density is improved, but parasitic elements increase and affect circuit performance
Solution Approach 1:
The patent changes the voltage parameter to compensate for the increased parasitic effects resulting from reduced wiring dimensions. By operating the cell array at a higher first supply voltage, the circuit overcomes the increased resistance and capacitance from scaled-down wirings, maintaining signal integrity and performance despite higher integration density.
3Productivity
If a single high supply voltage is used for all circuits, then performance is improved, but energy consumption increases
Solution Approach 1:
The memory device dynamically assigns different voltage levels to different functional blocks based on their performance requirements. The cell array operates at higher voltage for fast access, while peripheral circuits operate at lower voltage for power efficiency. This dynamic voltage assignment allows the system to achieve high performance where needed while minimizing overall energy consumption.
Data Source
AI summary
A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.