Dual-Voltage Word Line Driver With Timed PMOS Precharge
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Solution Overview
Problem
The reliability of semiconductor devices with CMOS gate-based word line drivers is compromised due to dielectric breakdown in MOS transistors caused by high voltage application, leading to increased power consumption and reduced reliability.
Innovation Solution
A driving circuit configuration with a first inverter driven by a first power supply voltage and a second inverter driven by a higher power supply voltage, along with a PMOS transistor and NMOS transistor, where a second PMOS transistor is temporarily turned on in synchronization with the falling input signal to control current flow, reducing the risk of dielectric breakdown and through-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high voltage is applied to the word line driver to accurately read data from memory cells, then the reading accuracy is improved, but the MOS transistors suffer dielectric breakdown leading to reduced reliability
Solution Approach 1:
The word line driver is divided into two separate inverters: a first inverter driven by a low voltage (first power supply voltage) and a second inverter driven by a high voltage (second power supply voltage). This segmentation allows the high voltage to be applied only to the second inverter's MOS transistors temporarily, rather than continuously to all transistors, thereby reducing dielectric breakdown risk while maintaining the ability to output high voltage to the word line for accurate data reading.
Solution Approach 2:
The second PMOS transistor is temporarily turned on in synchronization with the falling edge of the input signal, creating a periodic action that lasts only during the transition period. This temporary high voltage application to the second inverter reduces the cumulative stress on MOS transistors compared to continuous high voltage application, thereby improving reliability while still achieving the necessary voltage levels for accurate reading during operational cycles.
2Reliability
If different driving voltages are applied to the first and second inverters to reduce dielectric breakdown, then reliability is improved, but the output signals rise at different times causing through-current increase
Solution Approach 1:
The second PMOS transistor is turned on in advance (in synchronization with the falling edge of the input signal) to pre-charge the gate of the first PMOS transistor. This preliminary action ensures that when the input signal transitions, both inverters are ready to switch their output signals simultaneously, preventing the timing mismatch that would otherwise cause through-current. The preliminary charging action compensates for the different voltage levels applied to the two inverters.
Solution Approach 2:
The second PMOS transistor acts as an intermediary element between the power supply and the first PMOS transistor gate. It temporarily provides an additional charging path that synchronizes the output signal transitions of both inverters despite their different driving voltages. This intermediary component mediates the timing difference caused by voltage asymmetry, preventing simultaneous conduction of PMOS and NMOS transistors and thereby reducing through-current and power consumption.
Data Source
AI summary
According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.