Dual Voltage Select Gate Structure for NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face program disturb issues due to capacitive coupling between storage elements, particularly as NAND technology scales, leading to shifts in threshold voltage and potential read errors.
Innovation Solution
The implementation of dual voltage select gate structures, which include a coupling electrode and a select gate controllable by separate voltages, helps reduce program disturb by altering the depletion condition and increasing electron scattering, thereby minimizing the impact of capacitive coupling during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND technology is scaled to increase storage density, then storage capacity is improved, but program disturb increases due to capacitive coupling between storage elements
Solution Approach 1:
A coupling electrode is introduced as an intermediary component between the select gate and the storage elements. This coupling electrode serves as a mediator to control the electric field distribution and reduce capacitive coupling effects between adjacent storage elements during programming operations, thereby mitigating program disturb while maintaining high storage density
Solution Approach 2:
The patent applies separate voltage control to the select gate and coupling electrode, enabling independent adjustment of their respective electric field strengths. By changing voltage parameters dynamically during programming, the system can optimize the depletion condition and electron scattering to minimize program disturb effects on scaled storage elements
2Object-affected harmful factors
If capacitive coupling between storage elements is reduced, then program disturb is minimized, but device complexity increases due to additional control structures
Solution Approach 1:
The coupling electrode structure serves multiple functions simultaneously: it acts as a control element for reducing program disturb, functions as part of the select gate mechanism, and helps manage electric field distribution across the storage array. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity
Solution Approach 2:
The patent merges the coupling electrode with the select gate structure, combining what could be separate components into an integrated unit. This merging approach allows the system to achieve program disturb reduction through dual voltage control while avoiding the complexity of fully independent separate structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual voltage select gate structure effectively reduces Gate Induced Drain Lowering (GIDL) program disturb and maintains accurate threshold voltage levels, enhancing the reliability of non-volatile memory devices by minimizing the effects of capacitive coupling between storage elements.
Implementation Method 1
The implementation of dual voltage select gate structures, which include a coupling electrode and a select gate controllable by separate voltages, helps reduce program disturb by altering the depletion condition
Implementation Method 2
The implementation of dual voltage select gate structures, which include a coupling electrode and a select gate controllable by separate voltages, helps reduce program disturb by altering the depletion condition and increasing electron scattering
Implementation Method 3
Non-volatile memory devices face program disturb issues due to capacitive coupling between storage elements, particularly as NAND technology scales, leading to shifts in threshold voltage
Data Source
AI summary
A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.