Dual Voltage Select Gate Structure for NAND Memory Program Disturb
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Solution Overview
Problem
Non-volatile memory devices face program disturb issues due to capacitive coupling between storage elements, particularly in NAND technology, where shifts in threshold voltage occur during programming, leading to read errors and widened voltage distributions as the spacing between elements decreases with scaling.
Innovation Solution
The implementation of a dual voltage select gate structure, comprising a first and second conductive portion with a dielectric portion in between, and a coupling electrode, which reduces program disturb by controlling voltages applied to the select gate and coupling electrode to divert hot electrons and scatter charge effectively, thereby minimizing the impact of capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between storage elements is decreased to increase memory density, then memory capacity is improved, but program disturb increases due to capacitive coupling
Solution Approach 1:
A coupling electrode is introduced as an intermediary structure between the select gate and adjacent storage elements. This coupling electrode serves as a mediator to control and reduce capacitive coupling effects, thereby minimizing program disturb to non-selected storage elements while allowing the spacing between elements to be reduced for increased memory capacity.
Solution Approach 2:
The patent applies voltage control mechanisms by adjusting the voltage levels on the coupling electrode and select gate dynamically during programming operations. By changing voltage parameters (applying specific voltages to coupling electrode and select gate), the patent reduces the harmful capacitive coupling effects that cause program disturb, enabling closer spacing between storage elements without sacrificing reliability.
2Productivity
If programming voltage is increased to improve programming speed, then productivity is improved, but program disturb increases due to hot electron generation
Solution Approach 1:
The patent converts the harmful effect of high voltage (which generates hot electrons causing program disturb) into a beneficial control mechanism. By applying controlled voltages to the coupling electrode, the patent uses electric field effects to redirect and scatter hot electrons away from non-selected storage elements, thereby maintaining fast programming speeds while reducing program disturb.
3Ease of manufacture
If a single select gate structure is used to simplify device complexity, then ease of manufacture is improved, but program disturb control is insufficient
Solution Approach 1:
The select gate structure is segmented into two functional parts: a select gate for selecting storage elements and a coupling electrode for controlling capacitive coupling effects. This segmentation allows each component to perform its specific function optimally - the select gate maintains simplicity while the coupling electrode provides enhanced program disturb control, balancing ease of manufacture with improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual voltage select gate structure effectively reduces Gate Induced Drain Lowering (GIDL) program disturb, allowing for lower programming voltages and improved data integrity by reducing electron accumulation on adjacent storage elements, thus enhancing the reliability and efficiency of programming and reading operations.
Implementation Method 1
A dielectric portion is formed over a second part of the first conductive portion and a third conductive portion is formed over the dielectric portion. The third conductive portion is electrically isolated from the first conductive portion by the dielectric portion
Implementation Method 2
Non-volatile memory devices face program disturb issues due to capacitive coupling between storage elements
Implementation Method 3
controlling voltages applied to the select gate and coupling electrode to divert hot electrons and scatter charge effectively
Implementation Method 4
The dual voltage select gate structure effectively reduces Gate Induced Drain Lowering (GIDL) program disturb, allowing for lower programming voltages and improved data integrity by reducing electron accumulation on adjacent storage elements
Data Source
AI summary
A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.