Dual-Voltage Toggle Receiver Using Native VTH and Current Folding
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Solution Overview
Problem
Conventional ASIC receiver designs face challenges in supporting dual voltage operations (1.8V and 1.2V) due to operational voltage, technology, reliability, power, and performance limitations, particularly in maintaining high-speed operations and achieving reliable digital signal recovery with limited power budget.
Innovation Solution
The implementation of a high-speed toggle mode receiver architecture using native threshold voltage devices in differential amplifier circuits, including a low gain first stage, a transconductance tracking current source stage, a high gain second stage, and a duty cycle balancer circuit, which supports both 1.8V and 1.2V operations by maintaining devices in saturation and utilizing current folding for high gain digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker oxide devices are used to ensure reliable operations at 1.2V, then reliability is improved, but speed deteriorates
Solution Approach 1:
The patent changes the threshold voltage parameter of the input devices to a lower value (e.g., 0.4V to 0.6V) to enable high-speed operation at 1.2V while maintaining reliability. This is achieved through device design modifications such as using thinner oxide or adjusting doping profiles, allowing the devices to operate in the velocity saturation region for high-speed performance while remaining reliable at the lower voltage.
2Measurement precision
If higher AC gain is designed to digitize poor quality signals, then signal recovery quality is improved, but power consumption increases
Solution Approach 1:
The patent segments the amplification function into two distinct stages: a first differential amplifier stage providing moderate gain for initial signal conditioning, and a second differential amplifier stage providing high gain for final signal recovery. This segmentation allows the system to achieve the required overall AC gain while distributing power consumption across stages, with the second stage optimized for high gain at lower power due to the already-conditioned signal from the first stage.
Solution Approach 2:
The first differential amplifier stage provides partial amplification (moderate gain) to condition the input signal, reducing the burden on the second stage. This partial action approach allows the second stage to achieve high gain with lower power consumption than if a single stage attempted to provide all the gain, as the signal quality is already improved by the first stage.
3Reliability
If VTH of IO devices is high to ensure reliable operations, then reliability is improved, but headroom is constrained
Solution Approach 1:
The patent changes the threshold voltage parameter of the input devices to a lower value, which directly increases the headroom available for signal swing and biasing. This parameter change allows the devices to maintain reliability through proper biasing and operating point selection while providing sufficient headroom for high-speed operation and large signal swings required for robust signal recovery.
Data Source
AI summary
Storage devices are capable of utilizing receiver devices with native devices configured to support lower voltage supplies for higher read performances. The receiver device may include a current source circuit, first and second stage circuits, and a duty cycle balancer circuit. The first stage circuit may utilize first and second native devices with a threshold voltage (VTH) that enables proper lower voltage operations in saturation at high speeds. The current source stage circuit may utilize a third native device to track a transconductance and provide a reference current that becomes proportional to VTH to maintain tighter gain across process, variation, and temperature (PVT). The second stage circuit may utilize a current folding stage to provide a high gain for faster conversion of intermediate signals. The duty cycle balancer may utilize a fourth native device to balance a rise and fall delay skew across the PVT to maintain tighter duty cycle.