Dual Watchdog Timer Circuit for Abnormal Sub CPU Reset
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Solution Overview
Problem
Conventional information processing apparatuses cannot reset the system when the sub CPU abnormally operates, as the WDT circuit fails to deliver an interrupt signal to the reset circuit.
Innovation Solution
Incorporating a first WDT circuit set to a shorter timer time and a second WDT circuit set to a longer timer time, with the ability to extend the second timer time, allowing for controlled rebooting and resetting of the system when the sub CPU malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single WDT circuit is used to detect main CPU abnormalities, then the system can reset when the main CPU fails, but the system cannot reset when the sub CPU fails because the sub CPU cannot deliver interrupt signals when abnormal
Solution Approach 1:
The single WDT circuit is divided into two separate WDT circuits: the first WDT circuit detects abnormalities in the main CPU, and the second WDT circuit detects abnormalities in the sub CPU. Each WDT circuit operates independently with its own timer time setting, allowing the system to detect and respond to failures in either CPU without requiring the abnormal CPU to generate interrupt signals.
Solution Approach 2:
The WDT circuits serve as intermediary detection mechanisms that monitor CPU operations without relying on interrupt signals from the monitored CPUs. When a CPU fails, the WDT circuit detects the absence of periodic reset signals and triggers system reset independently, bypassing the need for the abnormal CPU to communicate its failure state.
2Reliability
If the second timer time is extended to allow for reboot processes, then the system can complete reboot operations before resetting, but the time required for system recovery increases
Solution Approach 1:
The system performs preliminary actions by extending the second timer time to allow the main CPU to execute reboot processes and data storage operations before the final system reset occurs. This preliminary period ensures that critical data is saved and the system is in a stable state before resetting, preventing data loss and ensuring orderly shutdown procedures.
Solution Approach 2:
The extended second timer time acts as a cushion period that provides a buffer between detecting the sub CPU abnormality and executing the final system reset. This cushion time allows the system to perform necessary recovery operations, store critical data, and attempt reboot procedures without immediately resetting, thereby reducing the risk of data loss while managing the overall recovery time.
Data Source
AI summary
An information processing apparatus capable of resetting the system when a sub CPU abnormally operates. A controller includes a main CPU for controlling operation of the system and a sub CPU for controlling operation of specific internal devices. A first WDT circuit and a second WDT circuit are set to a first timer time and a second timer time according to respective reset signals received from the sub CPU. According to a first interrupt signal output from the first WDT circuit based on expiration of the first timer time, the second timer time is controlled to be extended to a predetermined time and execution of a process for rebooting the controller is controlled. According to a second interrupt signal output from the second WDT circuit based on expiration of the extended second timer time, execution of a process for resetting the system is controlled.