Dual-Width Bus Inversion Voting Logic for Lower Signal Transitions
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Solution Overview
Problem
Existing majority voting logic schemes for data bus inversion do not account for multiple bus widths, leading to inefficient power management and increased power consumption due to unnecessary signal transitions.
Innovation Solution
A circuit that compares current and next bus values and determines bus inversion based on the number of changed bits, considering the indicated bus width, using XOR gates and full adder circuits to minimize transitions and support both ×8 and ×16 bus modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bus inversion is used to reduce power consumption, then power consumption decreases, but the system complexity increases due to the need for majority voting logic that accounts for multiple bus widths
Solution Approach 1:
The majority voting logic dynamically adapts to different bus widths (×8 or ×16) by receiving a width indication signal and adjusting its voting threshold accordingly. The circuit uses multiplexers and conditional logic to reconfigure the voting mechanism based on the active bus width, allowing the same hardware to efficiently reduce power consumption across multiple operating modes without requiring separate dedicated circuits for each width.
Solution Approach 2:
The system changes the voting parameter (threshold) based on the bus width indication. For ×8 mode, the threshold is set to 5 votes; for ×16 mode, the threshold is set to 9 votes. This parameter adaptation allows the majority voting logic to maintain effectiveness in reducing bus transitions and power consumption while accommodating different bus widths, resolving the contradiction between power savings and system complexity.
2Productivity
If the bus width is increased to ×16 for higher data throughput, then productivity increases, but the number of signal transitions increases leading to higher power consumption
Solution Approach 1:
The system implements feedback through the width indication signal that informs the majority voting logic of the active bus width. This feedback mechanism allows the voting circuit to adjust its behavior dynamically - when operating in ×16 mode with higher data throughput, the circuit knows to use a higher voting threshold (9 votes), thereby optimizing the balance between maintaining throughput and minimizing unnecessary bus transitions that would increase power consumption.
3Device complexity
If the bus width is reduced to ×8 to reduce the number of lines and save board area, then device complexity decreases, but the data throughput is reduced
Solution Approach 1:
The majority voting logic circuit is designed with universal functionality to support both ×8 and ×16 bus widths through a single unified circuit design. By incorporating width indication signals and conditional logic, the same hardware structure can adapt to different bus widths, allowing the system to reduce device complexity and board area when using ×8 mode while still maintaining the power optimization benefits of majority voting, and scaling to ×16 mode when higher throughput is required.
Data Source
AI summary
A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.