Dual Width Gate Electrode for Parasitic Capacitance Reduction
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Solution Overview
Problem
Current semiconductor devices face a trade-off between AC and DC performance due to increased parasitic capacitance in ultrathin FDSOI technology, which affects the efficiency of integrated circuits.
Innovation Solution
A high-k dielectric metal gate transistor design with a cascaded gate profile is implemented, where a conformal protective layer is used to increase the distance between the gate electrode and raised source/drain regions, reducing parasitic capacitance while maintaining overlap, achieved through a two-step etching process and deposition of a molecular layer deposition layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If raised source/drain regions are used to reduce external resistance in ultrathin FDSOI devices, then contact resistance is reduced, but parasitic capacitance between gate and source/drain regions increases
Solution Approach 1:
The gate electrode is designed with a dual-width structure where the lower portion has a greater width than the upper portion. This dimensional change in the gate structure increases the distance between the gate and raised source/drain regions in the vertical dimension, thereby reducing parasitic capacitance while maintaining effective overlap for device control
Solution Approach 2:
The gate electrode exhibits different widths at different vertical positions - a wider lower portion for reduced capacitance and a narrower upper portion for maintaining overlap. This local variation in geometric properties optimizes both AC and DC performance characteristics
2Productivity
If gate length is increased to boost DC performance, then device performance improves, but parasitic capacitance cannot be reduced due to manufacturing constraints
Solution Approach 1:
The gate electrode is segmented into two distinct width portions - an upper portion and a lower portion with different widths. This segmentation allows independent optimization of capacitance reduction (lower portion) and device performance (upper portion) without mutual interference
Data Source
AI summary
A high-k dielectric metal gate (HKMG) transistor includes a substrate, an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above the substrate. The gate electrode layer has an upper portion and a lower portion. A first liner contacts a sidewall portion of the upper portion. A spacer contacts the first liner and a sidewall portion of the lower portion. Raised source and drain regions are positioned adjacent the spacer. A height of the uppermost surface of the spacer is greater than a height of an uppermost surface of the raised source and drain regions. A width of the upper portion between the raised source and drain regions is smaller than a width of the lower portion between the raised source and drain regions.