Dual-width Trench Isolation on SOI Substrates
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Solution Overview
Problem
Deep trench isolation in Semiconductor-On-Insulator (SOI) devices faces a trade-off between achieving low resistance substrate contact and high voltage isolation, as increasing dielectric thickness for better isolation narrows the conductive plug, increasing resistance, while wider trenches increase defect likelihood and die size.
Innovation Solution
The solution involves forming two separate trenches with different widths: a wide trench for low resistance substrate contact and a narrow trench for high voltage isolation, allowing for independent optimization of these parameters with minimal fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric thickness is increased to improve voltage isolation, then the voltage isolation is improved, but the conductive plug width is narrowed which increases substrate connection resistance
Solution Approach 1:
The single trench structure is segmented into two separate trenches: a first trench optimized for voltage isolation with sufficient dielectric thickness, and a second trench optimized for substrate connection with adequate width for low resistance. This segmentation allows independent optimization of each function without the trade-off present in a single trench design.
2Manufacturing precision
If the trench width is increased to reduce substrate connection resistance, then the substrate connection resistance is reduced, but the die size area and defect level are increased
Solution Approach 1:
The trench structure is divided into two separate trenches with different width optimizations. The second trench is widened specifically for low resistance substrate connection, while the first trench maintains a narrower profile for voltage isolation, thereby reducing the overall die size compared to a single wide trench approach.
3Manufacturing precision
If the trench width is increased to reduce substrate connection resistance, then the substrate connection resistance is reduced, but the defect level due to dislocation faults is increased
Solution Approach 1:
The structure is segmented into two trenches where the second trench can be optimized for low resistance connection with appropriate width, while the first trench provides voltage isolation. This segmentation allows the connection trench to be optimized for conductivity without necessarily increasing overall defect levels, as the isolation trench can be positioned to minimize dislocation fault impact.
Data Source
AI summary
An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.