Dual Wordline Memory Access Concurrent Read Write Operations
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Solution Overview
Problem
Traditional memory compilers are inefficient and prone to accuracy errors in generating physical layout designs for memory circuitry, particularly in handling leakage, timing, power, and noise data, and often require costly and time-consuming processes that are sensitive to the number of rows in bitcells and wordline drivers, limiting the efficiency of read and write access operations.
Innovation Solution
Implementing a dual wordline circuitry system that allows concurrent read and write operations using the same wordline, with control logic to manage write pulse width and error rates, and utilizing fixed delays in self-timed paths to enhance write error rates without impacting read operations, thereby improving the endurance and efficiency of memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory compilers analyze error prone memory instances related to entire memory circuits, then comprehensive memory analysis is achieved, but the process becomes costly, time consuming and inefficient
Solution Approach 1:
The patent segments the memory circuit analysis into individual memory instance analyses. Instead of analyzing entire memory circuits at once, the system analyzes each memory instance separately using configuration data, which reduces the computational complexity and time required while maintaining analysis accuracy.
Solution Approach 2:
The patent performs preliminary actions by using configuration data to generate physical layout designs before actual memory operations. This preliminary design phase allows for early detection and correction of potential issues, reducing the need for time-consuming iterative analysis of entire circuits later.
2Quantity of substance
If memory instances are sensitive to a number of rows in bitcells and wordline drivers, then design accuracy is affected, but increasing row numbers improves memory capacity
Solution Approach 1:
The patent applies local quality by optimizing the design of individual memory instances based on their specific row configurations. Each memory instance can be tailored with appropriate row numbers, bitcell arrangements, and wordline driver configurations to achieve both desired capacity and design accuracy without being constrained by overall circuit sensitivity.
Solution Approach 2:
The patent utilizes parameter changes by allowing flexible configuration of row numbers, column numbers, and cell counts in memory instances. This enables the system to adjust parameters to find optimal configurations that balance memory capacity with design accuracy, overcoming the sensitivity issue through parameter optimization.
3Productivity
If dual wordline architecture is implemented for concurrent read and write operations, then memory access efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges read and write operations into a unified dual wordline architecture where both operations share common circuitry and control mechanisms. By combining the functionality of separate read and write paths into an integrated system with shared resources, the patent achieves concurrent operations without proportionally increasing overall device complexity.
Solution Approach 2:
The patent implements universality by designing the dual wordline architecture to handle multiple functions (read, write, and concurrent operations) through a single integrated system. The same physical infrastructure supports different operation types, reducing the need for separate dedicated circuits for each function and thereby limiting complexity growth.
Data Source
AI summary
Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.