Dual Wordline Memory Architecture for Area Efficiency

Solution Overview

Problem

Modern circuit architectures face inefficiencies in implementing multiple wordline schemes, leading to increased area and reduced performance in memory applications due to additional metal layers and capacitance.

Innovation Solution

The implementation of dual wordline schemes using both frontside and buried backside conductive lines, along with optimized timing designs, to enhance area efficiency, speed, and performance in memory applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple metal layers are used to provide multiple different wordlines, then wordline functionality is improved, but area increases and performance slows due to additional layers

Engineering Contradiction:

Improvewordline functionalityVSAvoidmemory area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the third dimension (vertical stacking) by forming bitcells at different depths within the semiconductor substrate. First bitcells are formed at a first depth with first wordlines, while second bitcells are formed at a second depth with second wordlines. This vertical differentiation allows multiple wordline functionalities to coexist without requiring additional lateral metal layers, thereby maintaining area efficiency while providing enhanced wordline adaptability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple metal layers are used to provide multiple different wordlines, then wordline functionality is improved, but performance slows due to added capacitance from additional conductive layers

Engineering Contradiction:

Improvewordline functionalityVSAvoidmemory performance

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent utilizes the third dimension (vertical stacking) by forming bitcells at different depths within the semiconductor substrate. First bitcells are formed at a first depth with first wordlines, while second bitcells are formed at a second depth with second wordlines. This vertical differentiation allows multiple wordline functionalities to coexist without requiring additional lateral metal layers, thereby maintaining area efficiency while providing enhanced wordline adaptability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If additional metal layers are added frontside, then more wordlines can be provided, but memory speed reduces due to added capacitance

Engineering Contradiction:

Improvewordline capabilityVSAvoidmemory speed

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

Instead of adding more metal layers on the frontside to provide additional wordlines, the patent inverts the approach by forming second bitcells and second wordlines at a greater depth within the substrate, beneath the first bitcells and first wordlines. This inversion of the conventional layering approach eliminates the need for additional frontside metal layers, thereby reducing parasitic capacitance and maintaining high memory speed while still providing enhanced wordline capability through the vertical stacking architecture.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20250140310A1Dual Wordline Applications in Memory

Publication Date: 2025.05.01 ARM LTD

AI summary

Various implementations described herein are directed to a device having an array of bitcells with a first bitcell disposed adjacent to a second bitcell. The device may have a first wordline coupled to first transistors in the first bitcell, and the device may have a second wordline coupled to second transistors in the second bitcell. Also, the device may have a buried ground line coupled to the first transistors and the second transistors.