Dual Work Function Semiconductor Device Gate Etching
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Solution Overview
Problem
In CMOS technology, the integration of NMOS and PMOS transistors with different gate metal stacks poses challenges during etching due to differences in stack materials and heights, leading to over-etching and formation of recesses or notches in Si and STI regions.
Innovation Solution
A method involving a substrate with distinct areas for NMOS and PMOS transistors, where a dielectric layer and metal layers with work function-shifting elements are used, followed by an anneal step to drive diffusion, allowing for a single metal gate and simplified gate etching process with a single final gate height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metal stacks are used for NMOS and PMOS transistors to achieve different effective work functions, then the required work function differentiation is obtained, but the gate etching process becomes complex and causes over-etching and formation of recesses or notches
Solution Approach 1:
The patent merges the gate structures of NMOS and PMOS transistors by forming a common gate electrode layer that spans both transistor types. This single gate structure is then selectively removed in different areas through a unified etching process, eliminating the need to handle different metal stacks separately and avoiding the complexity of simultaneous etching on different stack heights.
Solution Approach 2:
The patent performs preliminary actions by forming the complete gate electrode layer across both NMOS and PMOS areas before any selective removal. The gate electrode is deposited as a continuous layer with uniform thickness, establishing a baseline structure that can subsequently be selectively removed to create the desired dual-work-function configuration without dealing with complex simultaneous etching processes.
2Reliability
If different stack heights are used for NMOS and PMOS gates, then different work functions are achieved, but etching results in over-etching of Si and STI regions and formation of foot or notch defects
Solution Approach 1:
The patent combines the gate structures into a single unified layer with uniform height across both NMOS and PMOS regions. This eliminates the stack height difference problem entirely, as both transistor types now have gates at the same elevation, allowing a single etching process to define both gate structures simultaneously without causing over-etching or foot/notch defects.
Solution Approach 2:
While the gate electrode layer has uniform properties globally, the patent applies local quality by selectively removing the gate material in specific areas after formation. The selective removal process creates different final gate configurations for NMOS and PMOS based on local requirements, while the initial uniform formation avoids the precision problems associated with different stack heights.
3Ease of manufacture
If a single metal gate is used for both NMOS and PMOS, then manufacturing complexity is reduced, but different work functions must be achieved through alternative means
Solution Approach 1:
The patent segments the unified gate electrode layer into different functional regions after formation. By selectively removing portions of the gate electrode over specific transistor areas, the single gate structure is divided into functionally distinct regions that provide different work functions for NMOS and PMOS, maintaining manufacturing simplicity while achieving the required electrical differentiation.
Solution Approach 2:
The patent changes physical parameters of the gate structure through selective removal rather than changing material composition. By controlling the presence or absence of gate material in different areas, the effective work function is adjusted locally while maintaining a uniform gate electrode material throughout, simplifying the fabrication process compared to depositing different metal stacks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the gate definition and etching process, minimizing integration challenges by achieving a single final gate height for both NMOS and PMOS transistors, reducing complexity and potential defects like foot formation during etching.
Implementation Method 1
performing an anneal step adapted for driving diffusion of the first work function-shifting elements and the second work function-shifting elements into the dielectric layer
Data Source
AI summary
A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas.