Dual Work Function Gate Stack Tuning via Thermal Intermixing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down MOSFETs due to exponential gate direct tunneling currents with traditional SiO2 gate dielectrics and polysilicon gates, which are mitigated by high-k dielectrics and metal gates, but implementing dual work functions for CMOS devices is complex, especially achieving PMOS band-edge work functions at low equivalent oxide thickness.
Innovation Solution
A method for manufacturing dual work function semiconductor devices involves defining isolated regions for PMOS and NMOS transistors, using thermal treatment to modify gate dielectric stacks, and applying metal gate electrodes, which allows for tuning of effective work functions without significantly increasing oxide thickness, using high-k dielectrics and metal gate electrodes with specific capping layers to achieve desired work functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If high-k dielectrics and metal gates are introduced to reduce gate leakage currents, then gate direct tunneling currents are reduced, but the complexity of achieving dual work functions for CMOS devices increases
Solution Approach 1:
The patent applies local quality by forming different gate dielectric stacks in different regions of the semiconductor device. Specifically, a first gate dielectric stack with a first work function is formed in a first region, and a second gate dielectric stack with a second work function is formed in a second region. This allows each region to have locally optimized dielectric properties tailored to specific device requirements, enabling dual work function implementation without requiring completely separate fabrication processes.
Solution Approach 2:
The patent utilizes parameter changes by modifying the composition and structure of gate dielectric stacks to achieve different work functions. By varying the dielectric materials, layer thicknesses, and stacking configurations, the effective work function can be tuned independently in different regions. This approach allows continuous adjustment of electrical parameters without changing the fundamental device architecture.
2Manufacturing precision
If metal gate electrodes are used to eliminate polysilicon depletion effect, then threshold voltage control is improved, but tuning of work function becomes difficult as it is a material property
Solution Approach 1:
The patent employs composite materials by creating gate dielectric stacks composed of multiple dielectric layers with different properties. These composite structures combine materials with different work functions and dielectric constants, allowing the overall stack to exhibit a tailored effective work function. The composite nature enables continuous tuning of electrical characteristics while maintaining the benefits of metal gate electrodes.
Solution Approach 2:
The patent achieves universality by developing a gate dielectric stack structure that can serve multiple functions simultaneously. The same basic stack architecture can be configured to provide different work functions for different device types (e.g., nMOS and pMOS), eliminating the need for completely separate processing lines. The structure provides both the low leakage benefits of high-k dielectrics and the tunable work function capability traditionally associated with polysilicon.
3Adaptability or versatility
If selective removal of metal gates is performed to achieve dual metal gates, then different work functions can be obtained, but the manufacturing process complexity and costs increase substantially
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct regions with different gate dielectric configurations. Each region is independently configured during the fabrication process to have the appropriate work function, eliminating the need for post-fabrication selective removal steps. The segmentation is achieved through spatially selective deposition and processing techniques that pattern different dielectric stacks in different areas.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the gate dielectric stacks with the correct work function characteristics during the main fabrication process flow. Rather than starting with a single gate structure and selectively removing portions, the appropriate dielectric configurations are established upfront through selective deposition, annealing, or material modification steps performed on different regions simultaneously or in sequence during normal manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration process, reduces the number of steps, and effectively tunes the work functions for both PMOS and NMOS transistors, achieving desired threshold voltages and reliability, including enhanced negative bias temperature instability beyond 10 years at low equivalent oxide thickness.
Implementation Method 1
performing a thermal treatment of the first gate dielectric stack so as to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first effective work function
Data Source
AI summary
A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.