Dual Work Function Metal Gate Integration via Lanthanide and Group IIIa Dopants
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Solution Overview
Problem
Current methods for fabricating dual work function metal gates for CMOS devices face challenges in achieving precise work function adjustments and high dielectric constant values, which affect the performance and scalability of transistors.
Innovation Solution
The use of lanthanide series dopants like Yb and Group IIIa series dopants like Ga in the gate dielectric and gate electrodes of PMOS and NMOS transistors, respectively, to adjust the work function and increase the dielectric constant, combined with the formation of fully silicided gate electrodes, enhances the transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal gate fabrication methods are used, then manufacturing simplicity is maintained, but work function precision and dielectric constant are insufficient
Solution Approach 1:
The patent applies local quality by using different dopants for different transistor types: lanthanide series dopants (e.g., Yb) for PMOS gates and Group IIIa series dopants (e.g., Ga) for NMOS gates. This localized differentiation enables precise work function tuning for each transistor type while maintaining a unified fabrication process flow, thus improving manufacturing precision without significantly increasing overall device complexity.
Solution Approach 2:
The patent employs parameter changes by varying dopant concentration and type to achieve desired work function values. By controlling the amount of lanthanide or Group IIIa dopants incorporated into the metal gate during deposition, the work function can be precisely adjusted. Additionally, the dielectric constant is enhanced by selecting specific high-k dielectric materials and optimizing their thickness, thereby improving electrical characteristics without requiring fundamentally new fabrication approaches.
2Reliability
If high dielectric constant materials are used, then transistor performance is improved, but thermal budget increases causing undesirable effects
Solution Approach 1:
The patent replaces thermal processing with physical vapor deposition techniques to incorporate dopants into the metal gate. Instead of using high-temperature annealing to achieve dopant diffusion and work function adjustment, the invention uses magnetron sputtering or atomic layer deposition to directly implant dopants during gate formation. This substitution of mechanical/physical processes for thermal processes achieves the desired electrical characteristics while maintaining a low thermal budget, thus improving transistor performance without causing thermal damage to the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise tuning of work functions and increased dielectric constants, improving transistor performance and scalability, while minimizing thermal budget and avoiding undesirable effects on channel mobility and gate leakage.
Implementation Method 1
The use of lanthanide series dopants like Yb and Group IIIa series dopants like Ga in the gate dielectric and gate electrodes of PMOS and NMOS transistors, respectively, to adjust the work function
Implementation Method 2
increased dielectric constants, improving transistor performance and scalability
Implementation Method 3
combined with the formation of fully silicided gate electrodes, enhances the transistor performance
Data Source
AI summary
A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.