Dual Work Function Semiconductor Device Using Dielectric Capping Layers
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Solution Overview
Problem
The introduction of high-k materials in semiconductor devices leads to the Fermi level pinning effect, causing high threshold voltages in MOSFET devices, and existing solutions like metal gate materials are complex and costly to implement, while Fully Silicided gates suffer from threshold voltage non-uniformity on small devices.
Innovation Solution
A method for manufacturing dual work function semiconductor devices with a single metal gate electrode and dielectric capping layers, where a first dielectric capping layer on one region determines the effective work function of the second gate stack, and a second dielectric capping layer has no influence on it, with a metal layer selected to combine with the second capping layer to set the first effective work function, using Al-based and lanthanide-based dielectrics and nitridation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-k materials are introduced to replace SiO2 gate dielectric, then gate leakage is reduced, but Fermi level pinning effect occurs causing high threshold voltages
Solution Approach 1:
A dielectric capping layer is introduced as an intermediary between the high-k gate dielectric and the metal gate electrode. This capping layer mediates the interaction between high-k material and metal, preventing Fermi level pinning while maintaining the low gate leakage benefits of high-k materials. The capping layer acts as a buffer that eliminates the harmful interface effect between high-k dielectric and metal gate.
Solution Approach 2:
The gate stack is constructed as a composite structure comprising multiple layers: high-k gate dielectric layer, dielectric capping layer, and metal gate electrode layer. This composite structure combines the advantages of high-k materials (low gate leakage) with the benefits of metal gates (tunable threshold voltage), while the dielectric capping layer prevents the harmful interaction between high-k and metal components.
2Reliability
If metal gate materials are introduced to overcome Fermi level pinning, then threshold voltage control is improved, but manufacturing complexity and costs increase substantially
Solution Approach 1:
The gate structure is segmented into distinct functional layers: the high-k gate dielectric layer for electrical isolation and capacitance, the dielectric capping layer for interface protection and work function tuning, and the metal gate electrode layer for field control. This segmentation allows each layer to be optimized independently and formed using separate deposition processes, simplifying manufacturing compared to monolithic metal gate structures.
Solution Approach 2:
The dielectric capping layer serves multiple functions simultaneously: it prevents Fermi level pinning between high-k dielectric and metal gate, enables work function tuning for both NMOS and PMOS devices, provides a stable interface for metal deposition, and can be selectively removed or retained based on device type. This multi-functionality reduces the need for additional specialized layers and processes.
3Device complexity
If Fully Silicided gates are used to simplify manufacturing, then selective removal steps are eliminated, but threshold voltage non-uniformity increases on small devices
Solution Approach 1:
The dielectric capping layer is selectively present only in specific regions corresponding to PMOS devices, while being absent in NMOS regions. This local differentiation allows NMOS devices to have direct metal gate contact with the high-k dielectric for optimal n-type work function, while PMOS devices retain the capping layer for p-type work function tuning. This local quality approach enables precise threshold voltage control for each device type without compromising manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves manufacturability and reduces threshold voltage non-uniformity by independently establishing effective work functions for NMOS and PMOS regions, enhancing device performance and reducing manufacturing complexity and costs.
Implementation Method 1
the Fermi level pinning effect, originating in the interaction between high-k material and polysilicon
Implementation Method 2
a metal layer selected to determine in combination with the second dielectric capping layer the first effective work function
Data Source
AI summary
A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.