3D Memory Cell Structure with Dual Work Function Word Lines
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Solution Overview
Problem
Two-dimensional memory devices face limitations in increasing integration density due to the high cost and limitations of fine patterning techniques, prompting the need for three-dimensional memory devices with vertically stacked memory cells.
Innovation Solution
A semiconductor device with a three-dimensional structure featuring a thin active layer, dual word lines with low and high work function electrodes, and a dielectric capping layer to reduce parasitic capacitance and enhance integration density, while improving leakage current and threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cells with vertically stacked structure are adopted, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. The active layer is positioned above the substrate rather than directly on it, creating vertical stacking of source, channel, and drain regions. This dimensional change enables higher integration density by utilizing the vertical space above the substrate.
Solution Approach 2:
The word line is segmented into multiple functional components: a first word line with a first work function electrode and a second word line with a second work function electrode, separated by a dielectric layer. This segmentation allows independent control of different memory cell regions, managing the complexity through modular functional division while maintaining high integration.
2Manufacturing precision
If dual word lines with different work function electrodes are used, then threshold voltage control is improved, but manufacturing complexity increases
Solution Approach 1:
Different work function electrodes are applied to different word lines based on their specific functional requirements. The first word line uses a first work function electrode optimized for its operational characteristics, while the second word line uses a second work function electrode with different properties. This local optimization of material properties enables precise threshold voltage control for each memory cell region.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the first and second word lines with different work function electrodes. This dielectric mediator electrically isolates the two word lines while allowing both to be formed in the same vertical stacking structure, simplifying the manufacturing process by providing a clear separation interface.
3Quantity of substance
If vertically stacked memory cells are formed, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
A dielectric layer is positioned between the first and second word lines to act as an electrical insulator. This dielectric intermediary reduces the parasitic capacitance between the closely spaced word lines by providing high electrical resistance, while still allowing both word lines to be vertically stacked to achieve high memory cell density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases memory cell density, reduces parasitic capacitance, and improves refresh characteristics, leading to lower power consumption and higher integration density by forming a low electric field and high threshold voltage, thus overcoming the limitations of two-dimensional devices.
Implementation Method 1
a word line oriented laterally over the gate dielectric layer to face the active layer, and including a low work function electrode and a high work function electrode
Data Source
AI summary
A semiconductor device includes: an active layer including a channel which is spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line oriented laterally over the gate insulating layer to face the active layer, and including a low work function electrode and a high work function electrode which is parallel to the low work function electrode; and a dielectric capping layer disposed between the high work function electrode and the low work function electrode.