Dual Workfunction Gate Stacks Using Variable Metal Thickness
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing microelectronic devices due to issues with gate stack materials, particularly in achieving tunable work functions for metal-containing gate electrodes in CMOS technology, where high-energy ion implantation can damage dielectric layers and increase leakage current as feature sizes decrease.
Innovation Solution
A method for manufacturing dual workfunction semiconductor devices involves forming metal-containing gate electrode films with varying thicknesses over different device regions, using a combination of metal nitrides and metals like TiN and Ti, with a high-k dielectric film, to create gate stacks with adjustable work functions, reducing the risk of damage and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-energy ion implantation is used to lower the work function of metal gate electrode, then the work function is reduced, but the dielectric layer suffers charging damage leading to increased leakage current and decreased reliability
Solution Approach 1:
The patent changes the parameter of work function tuning from ion implantation energy to metal layer thickness. By depositing metal gate electrode layers with different thicknesses (e.g., 5nm for PMOS, 15nm for NMOS), the work function is adjusted without subjecting the dielectric layer to high-energy ion bombardment, thereby avoiding charging damage while achieving the required work function values for complementary MOS devices
Solution Approach 2:
The patent replaces the mechanical/physical process of ion implantation with a deposition process. Instead of bombarding the metal layer with high-energy ions to modify its properties, the patent uses physical vapor deposition or chemical vapor deposition to control the metal layer thickness, which in turn controls the work function. This substitution eliminates the harmful charging effects on the dielectric layer
2Reliability
If metal-containing gate electrode is used to replace doped poly-Si gate, then poly-Si depletion effect is eliminated and thermal stability is improved, but the work function becomes difficult to tune for different device regions
Solution Approach 1:
The patent applies local quality by creating different metal gate electrode thicknesses in different device regions. The metal layer is deposited with a thickness profile that is thinner over PMOS regions (e.g., 5nm) and thicker over NMOS regions (e.g., 15nm), allowing each device type to have the optimal work function while using the same metal material system throughout the chip
Solution Approach 2:
The patent introduces dynamics by making the metal gate electrode thickness variable rather than uniform. The thickness of the metal layer is dynamically adjusted across the substrate to match the different work function requirements of PMOS and NMOS devices, enabling post-deposition work function tuning without changing the material composition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of semiconductor devices with tunable work functions, reducing poly-Si depletion effects and improving thermal stability, while minimizing damage to the gate stack, thereby enhancing the reliability and performance of microelectronic devices.
Implementation Method 1
depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film
Data Source
AI summary
Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.