Dual Write Line SRAM Cell with Segmented Inversion
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Solution Overview
Problem
Designing robust SRAM semiconductor memories that can successfully write and read data across all operational voltage ranges is challenging due to increased instability and reduced write margins as device dimensions scale down, leading to higher rates of read disturbs and write failures.
Innovation Solution
The semiconductor memory storage device employs two data lines and two access control lines, using them together to write data, which increases the charge transfer effectiveness and reduces the need for additional voltage, thereby improving write success without increasing read failures. This configuration allows for a controlled access mechanism with a time delay for one data line to minimize disturbance to non-target cells during writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write assist mechanisms are used to increase voltage on the word line during write, then write success rate is improved, but the probability of read disturb to cells on the same row increases
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation using the first word line, and a second write operation using the second word line with inverted data values. This segmentation allows the system to achieve write assist benefits without the harmful side effects, as the second operation serves to correct and stabilize the write rather than amplify it.
Solution Approach 2:
The patent applies inversion by writing the complement (inverted) values to the second word line after the first write operation. This inversion technique allows the system to correct any incomplete writes and stabilize the stored values without requiring additional voltage boosting, thereby avoiding read disturb issues.
2Length of moving object
If device dimensions are scaled down, then device size is reduced, but variations in device properties increase causing increased read disturbs and reduced write margins
Solution Approach 1:
The patent performs a preliminary write operation using the first word line before attempting the final write. This preliminary action ensures that the storage cell is partially programmed and ready to receive the final write data, thereby improving write margins without requiring larger device dimensions.
Solution Approach 2:
The patent uses feedback by performing a second write operation with inverted values based on the outcome of the first write operation. This feedback mechanism allows the system to correct write errors and stabilize stored values, compensating for the increased variability caused by scaled-down dimensions.
3Length of moving object
If device dimensions are scaled down, then device size is reduced, but the rate of read disturbs increases
Solution Approach 1:
By segmenting the write operation into two phases using different word lines, the patent reduces the voltage spike duration and magnitude affecting any single cell, thereby reducing the likelihood of read disturbs in scaled-down devices.
Solution Approach 2:
The inversion technique applied in the second write operation stabilizes the stored values and reduces metastable states that could lead to read disturbs, which is particularly important in scaled-down devices where noise margins are reduced.
Data Source
AI summary
A semiconductor memory storage device with a plurality of storage cells, each cell includes two access control devices, each providing the cell with access to or isolation from a respective one of two data lines in response to an access control signal provided by access control circuitry. The control devices are controlled to provide the storage cell with access to or isolation from either of the first and second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines.