Dummy Active Trench Gate for dV/dt Control in Semiconductor Devices
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Solution Overview
Problem
The existing semiconductor devices with trench gate configurations, such as IGBTs, face challenges in controlling the rate of change of drain voltage (dV/dt) due to increased turn-on losses, particularly when the gate resistance is high, leading to reduced controllability and increased losses during low dV/dt conditions.
Innovation Solution
A semiconductor device configuration is introduced where a transistor and diode are formed on a common substrate, incorporating a diode region with a dummy active trench gate that extends from the semiconductor substrate's surface to the second semiconductor layer, with the third semiconductor layer on the side surfaces in a floating state and applied with a gate potential, enhancing the controllability of dV/dt and reducing turn-on losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dummy trench gates are provided between adjacent trench gates to increase gate-collector capacitance, then turn-on loss is reduced under constant dV/dt conditions, but gate-resistance controllability of dV/dt is reduced leading to increased turn-on loss in low dV/dt regions
Solution Approach 1:
The invention divides the dummy trench gate structure into segments with different potential applications. Specifically, it provides a first dummy trench gate with a first potential applied to its third semiconductor layer, and a second dummy trench gate with a second potential applied to its third semiconductor layer. This segmentation allows different portions of the dummy trench gates to serve different functions: some segments increase gate-collector capacitance while other segments maintain gate-resistance controllability of dV/dt.
Solution Approach 2:
The invention applies different potentials to different third semiconductor layers of the dummy trench gates, creating local quality variations. The first dummy trench gate's third semiconductor layer receives a first potential while the second dummy trench gate's third semiconductor layer receives a second potential. This local differentiation enables specific regions to optimize for capacitance enhancement while other regions maintain controllability, resolving the contradiction between reducing turn-on loss and maintaining gate-resistance controllability.
2Loss of energy
If gate resistance is increased to reduce turn-on loss under constant dV/dt, then dV/dt controllability is improved, but gate-resistance controllability is reduced
Solution Approach 1:
The invention segments the dummy trench gate system into multiple independently controllable units with different potentials. By providing a first dummy trench gate with a first potential and a second dummy trench gate with a second potential, the system can selectively activate or adjust different segments based on operating conditions. This allows optimization of turn-on loss in specific regions while maintaining gate-resistance controllability in other regions.
Solution Approach 2:
The invention enables dynamic control of dummy trench gate potentials by applying different potentials (first potential and second potential) to different third semiconductor layers. This dynamic configuration allows the system to adaptively adjust the balance between turn-on loss reduction and gate-resistance controllability based on real-time operating conditions, resolving the contradiction by making the system flexible rather than fixed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the controllability of dV/dt, thereby reducing turn-on losses in semiconductor devices by increasing the gate-collector capacitance, which helps in minimizing losses under constant dV/dt conditions.
Implementation Method 1
increasing gate-collector capacitance (feedback capacitance) Cgc between the gate and the collector of the IGBT
Data Source
AI summary
A diode region includes: an n-type first semiconductor layer provided on a second-main-surface side in the semiconductor substrate; an n-type second semiconductor layer provided on the first semiconductor layer; a p-type third semiconductor layer provided closer to a first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode that applies a first potential to the diode; a second main electrode that applies a second potential to the diode; and a dummy active trench gate provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer. The dummy active trench gate includes the third semiconductor layer that is not applied with the first potential to be in a floating state on at least one of two side surfaces, and the dummy active trench gate is applied with a gate potential of the transistor.