Memory System Cache Invalidation Using Dummy Address Space

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Solution Overview

Problem

Conventional methods for flushing and invalidating cache memory in hierarchical memory architectures are inefficient, particularly for large memory capacities, taking minutes or even hours, and lack effective strategies for cache coherence in multi-processor systems.

Innovation Solution

Implementing a dummy address space equal in size to the cache memory, allowing a single read operation to both flush and invalidate cache entries by reading from this space, which is not accessible by the operating system, ensuring cache coherence and reducing the time required for cache operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional cache flushing and invalidation methods are used, then cache coherence can be maintained, but the time required for cache operations becomes excessively long (minutes or hours) especially for large memory capacities

Engineering Contradiction:

Improvecache coherenceVSAvoidcache operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the address space into a dummy address space and a real address space. The dummy address space is specifically designed to map to all cache lines, allowing selective invalidation of cache entries without affecting real memory operations. This segmentation enables efficient cache flushing by targeting only the dummy address space, dramatically reducing the time required compared to conventional methods that must process the entire address space.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a dummy address space as an intermediary mechanism between the processor and the cache memory. This intermediary allows cache invalidation operations to be performed by accessing the dummy address space, which acts as a mediator that can flush cache entries without requiring direct manipulation of the entire real address space. The dummy address space serves as a buffer or intermediate layer that simplifies the cache flushing process.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the cache memory size increases to handle large memory capacities, then memory performance improves, but the time required for flushing and invalidating cache memory increases significantly

Engineering Contradiction:

Improvememory performanceVSAvoidcache invalidation time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a dummy address space that is a copy or replica of the address space structure, but specifically designed for cache management purposes. This dummy copy allows cache invalidation operations to be performed on the copy rather than on the actual data, enabling efficient flushing without disturbing real memory operations. The dummy address space serves as a sacrificial copy that absorbs the overhead of cache management operations.

Inventive Principle:

Principle #26Copying

3Loss of time

If a dummy address space is implemented to enable single read operations for cache flushing, then cache operation time is reduced, but device complexity increases due to additional address space management

Engineering Contradiction:

Improvecache flushing timeVSAvoidaddress space management complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The dummy address space is designed to serve multiple functions simultaneously: it acts as a mapping for all cache lines, provides a target for cache invalidation operations, and does not interfere with real memory operations. This multi-functionality allows the system to achieve efficient cache flushing without proportionally increasing complexity, as the dummy address space integrates seamlessly into the existing address space architecture rather than requiring separate management mechanisms.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP3757800B1Memory system, computing system, and methods thereof

Publication Date: 2025.10.08 INTEL CORP

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AI summary

According to various aspects, a memory system (100, 200) may include: a memory (110) having a memory address space (112) associated therewith to access the memory (110); a cache memory (120) assigned to the memory (110); one or more processors (130) configured to generate a dummy address space (132) in addition to the memory address space (112), each address of the dummy address space (132) being distinct from any address of the memory address space (112), and generate one or more invalid cache entries in the cache memory (120), the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space (132).