Dummy Bit Line Bias Circuit for Nonvolatile Memory Interference
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face interference issues between memory cells and dummy cells, leading to performance degradation and reliability concerns due to the lack of effective programming and verification mechanisms for dummy cells, which can result in over-programming or over-erasing, affecting adjacent memory cells.
Innovation Solution
The implementation of a dummy bit line bias circuit that provides a specific voltage to dummy cells during program and erase operations, controlling the threshold voltage of dummy cells to prevent interference by programming them into a dummy state between the erased and top programmed states, and using control logic to manage the bias operations and verify programming states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy cells are not programmed during normal program operations, then the memory device structure is simpler and manufacturing is easier, but interference occurs between dummy cells and normal memory cells causing reliability degradation
Solution Approach 1:
A dummy bit line bias circuit is introduced as an intermediary component to provide controlled voltage to dummy cells during program operations. This mediator prevents interference between dummy cells and normal memory cells by maintaining dummy cells in a non-interfering state, thereby improving data integrity without fundamentally changing the memory device structure.
Solution Approach 2:
The bias circuit dynamically changes the voltage parameter of the dummy bit line based on operation mode. During program operations, the dummy bit line is biased to a specific voltage level to prevent interference. During erase operations, the dummy bit line is maintained at a different voltage level. This parameter change approach resolves the reliability issue while avoiding permanent structural complexity.
2Reliability
If dummy cells are programmed to prevent interference, then reliability improves, but additional bias control circuits and complexity are introduced
Solution Approach 1:
The dummy bit line bias circuit is designed to serve multiple functions: during program operations, it prevents interference by biasing dummy cells; during erase operations, it maintains dummy cells in a floating state; and during read operations, it provides appropriate voltage levels. This multi-functionality reduces the need for separate dedicated circuits for each operation mode, thereby limiting the increase in overall device complexity while improving memory cell performance.
3Manufacturing precision
If dummy cells are left in floating state during erase operations, then programming control is simpler, but over-erasing may occur affecting adjacent normal cells
Solution Approach 1:
The bias circuit applies a preliminary counteracting voltage to the dummy bit line during erase operations to prevent over-erasing. By maintaining the dummy bit line at a controlled voltage level (different from program operations), the circuit preemptively counteracts the harmful effect of charge leakage from dummy cells to adjacent normal cells, thereby preventing over-erasing interference while keeping erase operation control relatively simple.
Data Source
AI summary
Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation.