Dummy Bit Line Parasitic Capacitance for SRAM Write Margin
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Solution Overview
Problem
Conventional write assist schemes in volatile memory elements, such as SRAM and CRAM cells, face reliability issues due to variability in negative bit line voltages caused by process-temperature-voltage (PVT) variations, leading to decreased read and write margins and potential data corruption, especially as semiconductor technology scales to smaller sizes and lower power supply voltages.
Innovation Solution
The implementation of a negative bit line write assist scheme using dummy bit lines to provide parasitic capacitance, which reduces variability and maintains effective write assist without area overhead, by forming dummy bit lines adjacent to active bit lines and adjusting their distance to maximize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write assist schemes are used in volatile memory elements, then write operations can be performed, but variability in negative bit line voltages due to PVT variations decreases reliability and write margin
Solution Approach 1:
The patent creates a copy of the active bit line structure by forming dummy bit lines adjacent to the active bit lines. These dummy bit lines are identical in structure and material composition but serve only to provide parasitic capacitance. The parasitic capacitance from the dummy bit lines couples to the active bit lines, stabilizing the negative bit line voltage during write operations and reducing variability caused by PVT variations, thereby improving write margin and reliability without adding area overhead.
2Productivity
If semiconductor technology scales to smaller sizes with lower power supply voltages, then device integration increases, but read and write margins decrease
Solution Approach 1:
The patent changes the electrical parameters of the bit line system by introducing parasitic capacitance from dummy bit lines. This parasitic capacitance modifies the voltage waveform characteristics during write operations, providing stronger drive capability and larger voltage swings on the active bit lines. This parameter change compensates for the reduced margins caused by scaling to smaller sizes and lower power supply voltages, maintaining reliable read and write operations despite increased device integration.
3Reliability
If dummy bit lines are formed adjacent to active bit lines to maximize parasitic capacitance, then negative bit line voltage stability improves, but die area increases
Solution Approach 1:
The patent merges the dummy bit lines with the active bit lines in the vertical dimension by forming them in the same metal layer and routing them adjacent to each other. This merging approach allows the dummy bit lines to provide parasitic capacitance while sharing the same physical space and routing infrastructure as the active bit lines. The close proximity maximizes parasitic capacitance coupling, and the integrated structure minimizes additional die area compared to separate dummy bit line structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the negative bit line voltage, reducing variability and improving device reliability while maintaining effective write performance without increasing die area, thus addressing the challenges of PVT variations and data corruption.
Implementation Method 1
The implementation of a negative bit line write assist scheme using dummy bit lines to provide parasitic capacitance, which reduces variability and maintains effective write assist
Data Source
AI summary
Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line. During data loading operations, at least one of the dummy data lines can be pulsed to temporarily drive the voltage on the associated data line to below the ground voltage level. Operated in this way, the write operation of the memory cells can be improved.