3D NAND Dummy Bit Line Layout for Short-Circuit Testing
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in efficiently detecting defects and ensuring high reliability while maintaining low costs and short testing times, particularly in three-dimensionally structured NAND flash memory systems.
Innovation Solution
The implementation of multiple dummy regions connected by common wiring allows for simultaneous testing and voltage application, enabling effective defect detection and reducing the complexity of testing processes, thereby enhancing reliability and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dummy regions are tested separately with individual wiring, then testing completeness is improved, but device complexity and testing time increase
Solution Approach 1:
Multiple dummy regions (first dummy region and second dummy region) are connected through a common dummy bit line, merging previously separate testing operations into a unified structure. This allows simultaneous testing of multiple dummy regions through shared wiring, reducing overall device complexity while maintaining testing completeness.
Solution Approach 2:
The common dummy bit line serves multiple functions: it connects both the first dummy region and the second dummy region, enabling a single wiring structure to perform what previously required separate wiring for each region. This multi-functional approach reduces wiring complexity while preserving the ability to test all dummy regions comprehensively.
2Reliability
If extensive testing procedures are implemented to detect all defects, then reliability is improved, but testing time and cost increase
Solution Approach 1:
Dummy regions are configured in advance with specific structures (stack structures with insulating films and conductive layers) that enable automatic defect detection during normal operation. The preliminary arrangement of these regions allows short circuit detection to occur naturally during manufacturing testing without requiring extensive additional testing procedures.
Solution Approach 2:
The dummy regions are designed to automatically indicate defects through their electrical characteristics when connected to the common dummy bit line. During testing, any short circuits or defects in the dummy regions self-reveal through the wiring structure, eliminating the need for complex external testing equipment or procedures while maintaining high defect detection accuracy.
3Device complexity
If dummy regions are not connected by common wiring, then wiring complexity is reduced, but testing efficiency and reliability decrease
Solution Approach 1:
The common dummy bit line merges the connection paths to multiple dummy regions, allowing a single wiring structure to serve multiple testing functions. This merging enables simultaneous access to both the first and second dummy regions, dramatically improving testing efficiency while the wiring complexity remains manageable due to the shared nature of the connection.
Data Source
AI summary
A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.