Dummy Memory Block Pool Capacitor for 3D NAND Power Noise
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Solution Overview
Problem
Conventional 3D NAND memory devices face challenges in maintaining stable power conditions due to insufficient space for pool capacitors in peripheral circuit regions as die size shrinks, leading to increased power noise and reduced memory density.
Innovation Solution
Incorporating dummy memory blocks as supplementary pool capacitors with an alternating layer stack of conductive and dielectric layers, where conductive layers are biased to power sources and ground potential, forming capacitors to suppress power noise, and these blocks are strategically placed at the outskirts of memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If die size is shrunk to increase memory density, then memory density is improved, but space for pool capacitors in peripheral circuit regions is reduced
Solution Approach 1:
The patent merges the function of pool capacitors with dummy memory blocks by integrating capacitor structures into the dummy block region. The alternating conductive and dielectric layers within the dummy block form capacitor structures that serve both as dummy blocks for memory array completeness and as pool capacitors for power noise suppression, eliminating the need for separate capacitor spaces in peripheral circuits.
Solution Approach 2:
The dummy block region is given multiple functions: it maintains the memory array structure for completeness, serves as a placeholder for potential future use, and simultaneously functions as a pool capacitor for power stabilization. This multi-functionality allows the same physical space to fulfill multiple roles, resolving the space conflict.
2Reliability
If pool capacitors are deployed in peripheral circuit regions to suppress power noise, then power stability is improved, but available die area is reduced
Solution Approach 1:
The patent combines the power stabilization function with the dummy block structure by forming capacitor structures using the alternating conductive and dielectric layers within the dummy block. This integration allows power noise suppression without requiring additional dedicated capacitor space, as the dummy block itself becomes the capacitor.
Solution Approach 2:
The dummy block structure serves itself by using its own internal layers (conductive and dielectric) to form capacitor structures that provide power stabilization. The existing structural elements of the dummy block are repurposed to provide the capacitive function, eliminating the need for separate capacitor components.
3Reliability
If conventional capacitor structures are used in peripheral circuits, then power noise suppression is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the capacitor manufacturing process with the existing dummy block fabrication process. The alternating conductive and dielectric layers are formed using the same deposition and patterning steps already required for the memory array, eliminating the need for separate capacitor fabrication processes and reducing overall manufacturing complexity.
Solution Approach 2:
The patent uses the same materials and structural approaches for the dummy block capacitors as are used for the functional memory cells. The alternating conductive and dielectric layer structure is consistent with the memory array architecture, allowing uniform processing conditions and simplifying manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances power stability and noise suppression, improving the reliability and performance of memory devices by effectively utilizing space within the memory arrays to support peripheral circuit operations.
Implementation Method 1
The alternating dummy layer stack comprises multiple conductive layers and multiple dielectric layers alternately laminated on one another... forming capacitors between the multiple conductive layers, wherein the multiple dielectric layers act as a capacitor dielectric
Implementation Method 2
The multiple conductive layers are configured to be sequentially and alternately biased to a power source and a ground potential via the contacts disposed on the stair structures
Data Source
AI summary
A non-volatile memory device includes a substrate, a plurality of memory blocks grouped into pages, each including an alternating layer stack on the substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, and at least one dummy block adjacent to the plurality of memory blocks, each including an alternating dummy layer stack having multiple conductive layers and multiple dielectric layers alternately laminated on one another on the substrate, the at least one dummy block is disposed at an outskirt of each of the pages of the plurality of memory blocks.