Dummy Bottom Electrode CMP Dishing Logic Region
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Solution Overview
Problem
Chemical mechanical polishing (CMP) in semiconductor manufacturing can cause 'dishing' of metal interconnect lines in logic regions due to the structural difference between bottom electrodes in memory regions and metal interconnect lines in logic regions, leading to unreliable integrated circuits.
Innovation Solution
A dummy bottom electrode is introduced above the metal lines in the logic region to act as a CMP stop, providing structural rigidity and preventing erosion during planarization, thereby maintaining uniformity of metal lines across the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing is performed to planarize the bottom electrode layer, then the bottom electrode surface is planarized, but the metal interconnect lines in the logic region suffer from dishing and erosion
Solution Approach 1:
A dummy bottom electrode is introduced as an intermediary structure in the logic region to act as a CMP stop. This dummy electrode has similar mechanical properties to the real bottom electrode, allowing it to protect the metal interconnect lines from excessive polishing while maintaining uniform planarization across the entire wafer surface.
Solution Approach 2:
The dummy bottom electrode is selectively placed only in the logic region where metal interconnect lines are located, while the memory region retains its normal bottom electrode structure. This local differentiation allows the CMP process to be controlled differently in different regions, preventing dishing in the logic region without affecting the memory region functionality.
2Shape
If the bottom electrode layer is planarized, then a flat surface is achieved, but the metal lines in logic regions become thinner due to erosion
Solution Approach 1:
The dummy bottom electrode serves as a mediator that absorbs the mechanical stress and polishing action during CMP, preventing the polishing pads from directly eroding the metal interconnect lines. This intermediary structure ensures that the metal lines maintain their original thickness while still achieving the desired surface flatness.
Solution Approach 2:
The dummy bottom electrode is prepared in advance in the logic region to provide cushioning protection before the CMP process begins. This pre-positioned protective structure prevents the metal lines from being exposed to direct mechanical polishing forces, thereby preventing thickness reduction before it can occur.
3Strength
If structural rigidity is increased in the logic region to prevent CMP erosion, then metal line protection is improved, but the device complexity increases
Solution Approach 1:
The additional structural element (dummy bottom electrode) is introduced only in the logic region where it is needed for protection, rather than throughout the entire device. This localized approach increases structural rigidity only where necessary, minimizing the overall increase in device complexity.
Solution Approach 2:
The dummy bottom electrode is essentially a copy of the real bottom electrode structure, using the same material composition and fabrication process. This copying approach allows the protective structure to be integrated into the existing manufacturing flow without requiring new materials or complex additional processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy bottom electrode effectively prevents CMP-induced erosion of metal lines in logic regions, ensuring more reliable and uniform metal interconnects, thus enhancing the integrity and performance of integrated circuits.
Implementation Method 1
Chemical mechanical polishing (CMP) in semiconductor manufacturing can cause 'dishing' of metal interconnect lines
Data Source
AI summary
The present disclosure relates an integrated circuit (IC). A plurality of metal layers is disposed within an inter-layer dielectric (ILD) material over the substrate. A memory cell is disposed over a first metal layer at a memory region and comprising a bottom electrode directly above a first metal line within the first metal layer and a top electrode separated from the bottom electrode by a resistance switching element. A dummy structure comprises a dummy bottom electrode arranged directly above a second metal line within the first metal layer at a logic region adjacent to the memory region.