Semiconductor Package Dummy Bump Layout for Coplanar Fine-Pitch Interconnects
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Solution Overview
Problem
The challenge in semiconductor packaging lies in maintaining uniformity and coplanarity of conductive bumps as dimensions and pitches shrink, leading to issues with electrical connections and structural integrity.
Innovation Solution
Incorporating dummy bumps around the periphery of the conductive bumps during the manufacturing process, formed through electroplating, to enhance uniformity and coplanarity, while maintaining electrical isolation from semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If dimensions and pitches of conductive bumps are reduced, then device integration is improved, but bump uniformity and coplanarity deteriorate
Solution Approach 1:
The patent applies local quality by forming dummy bumps with different properties than conductive bumps. The dummy bumps are electrically isolated while maintaining physical presence, creating localized structural support without electrical connectivity. This allows the periphery regions to have enhanced uniformity and coplanarity control through the dummy bump structures, while the central conductive bumps maintain their electrical function.
Solution Approach 2:
The dummy bumps act as intermediary structures between the conductive bumps and the underlying substrate. These intermediary dummy bump structures provide mechanical support and reference planes that help maintain coplanarity of the conductive bumps, especially as pitch dimensions are reduced. The dummy bumps mediate the mechanical stresses and provide a reference framework for uniform bump formation.
2Manufacturing precision
If dummy bumps are added around conductive bumps, then bump uniformity and coplanarity are improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of dummy bumps and conductive bumps into a single electroplating process step. Both types of bumps are formed simultaneously in the same process sequence, using the same plating chemistry and parameters. This merging approach reduces manufacturing complexity despite the increased structural complexity, as no additional process steps are required beyond the standard bump formation sequence.
3Manufacturing precision
If electroplating is used to form bumps, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent utilizes parameter changes in the electroplating process to differentiate between dummy bump and conductive bump formation. By adjusting plating parameters such as current density, plating time, and solution composition, the process can selectively form electrically isolated dummy bumps or electrically conductive bumps. This parameter control allows precise management of bump properties within a single electroplating process framework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves bump uniformity and coplanarity, enhances electrical connections, and reduces underfill overflow, thereby increasing yield and reducing manufacturing costs.
Implementation Method 1
Incorporating dummy bumps around the periphery of the conductive bumps during the manufacturing process, formed through electroplating
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.