Dummy-Capacitor Transistor Circuit for Secondary Nonlinearity

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Solution Overview

Problem

Conventional transistor circuits suffer from secondary nonlinearity due to parasitic components, which cause distortion in output signals, as they only account for sampling capacitors and not the full impact of parasitic resistances and capacitors in signal paths.

Innovation Solution

Incorporating a dummy capacitor or dummy transistor between the input terminal and the transistor, connected in series with parasitic resistors and capacitors, to reduce parasitic currents and improve signal linearity, thereby minimizing the effect of parasitic components and clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional transmission gate or dummy NMOS/PMOS transistor is used to prevent nonlinearity, then clock feedthrough is reduced, but secondary nonlinearity due to parasitic resistance remains

Engineering Contradiction:

Improvelinearity of output signalVSAvoidsecondary nonlinearity from parasitic resistance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A dummy capacitor is introduced as an intermediary element between the input terminal and the transistor. This dummy capacitor acts as a mediator to compensate for the voltage drop across the parasitic resistance, thereby eliminating secondary nonlinearity without affecting the main switching function of the transistor.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the electrical parameters of the circuit by adding a capacitor with a specific capacitance value. This parameter change allows the circuit to maintain a constant voltage at the input terminal despite variations in parasitic resistance,从而 improving linearity.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If only sampling capacitor is considered in designing transmission gate, then basic switching function is achieved, but secondary nonlinearity cannot be completely eliminated

Engineering Contradiction:

Improvesimplicity of circuit designVSAvoidelimination of secondary nonlinearity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The invention segments the input terminal voltage control into two independent parts: the sampling capacitor handles the basic switching function, while the dummy capacitor specifically addresses the secondary nonlinearity caused by parasitic resistance. This segmentation allows each component to be optimized for its specific function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of redesigning the entire transmission gate, the invention adds a partial solution (dummy capacitor) that specifically targets and eliminates the secondary nonlinearity issue without complicating the overall circuit design.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If dummy transistor is added to prevent nonlinearity, then clock feedthrough is reduced, but circuit complexity increases

Engineering Contradiction:

Improvereduction of clock feedthroughVSAvoidnumber of transistors in circuit

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention uses a capacitor (dummy capacitor) that replicates or copies the function of compensating for parasitic effects, rather than adding another active transistor. This copying approach achieves the desired effect with a simpler, passive component.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The dummy capacitor is a simple, passive, and inexpensive component compared to an active transistor. It performs its compensation function effectively without requiring complex biasing or control circuits, thus reducing overall device complexity.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces secondary nonlinearity, enhancing the performance of switched-capacitor circuits and reducing performance differences between channels and IC chips in multi-channel and multi-chip products, without the need for complex layout techniques like clock trees.

Implementation Method 1

a dummy capacitor with a first terminal connected to the connection line that is between the input terminal and the transistor

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a parasitic capacitor between (i) the input terminal or the connection line and (ii) the transistor or a signal line providing the clock signal

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS11038501B2Transistor circuit and electronic circuit having same

Publication Date: 2021.06.15 DB GLOBALCHIP CO LTD

AI summary

A transistor circuit having a dummy capacitor or a dummy transistor between an input terminal and a transistor is disclosed. The circuit improves secondary nonlinear characteristics of the transistor attributable to one or more parasitic components and a clock signal. The transistor circuit includes an input terminal configured to receive an input signal, a transistor having a gate configured to receive a clock signal, and a source connected to the input terminal, a connection line between the input terminal and the transistor and having a parasitic resistor therein, a parasitic capacitor between the input terminal and the transistor, and a dummy transistor having a first terminal that is connected to the connection line between the input terminal and the transistor.