Dummy Cell Latch Circuit for Semiconductor Leakage Reduction
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Solution Overview
Problem
The challenge of reducing power leakage in semiconductor devices, particularly in systems-on-chip (SoCs) with increasing transistor counts, is significant, especially in deep-micron technologies where sequential cells like scannable D flip-flops and data latches are used.
Innovation Solution
Incorporating leakage-free dummy cells in non-critical paths of master and slave latches within scannable D flip-flops and data latches, utilizing transistors with specific connections to reduce leakage current and improve operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistor count is increased to enhance functionality, then device capability is improved, but power leakage increases
Solution Approach 1:
The patent segments the sequential cell structure into master latch and slave latch portions, and introduces dummy cells as separate functional units that can be selectively activated. This segmentation allows the dummy cells to independently address leakage issues without interfering with the primary data storage function, thus reducing power leakage while maintaining device capability.
Solution Approach 2:
The dummy cells act as intermediary elements inserted into non-critical paths between the master and slave latches. These intermediary dummy cells capture and hold leakage current that would otherwise propagate through the circuit, thereby protecting the main data path from leakage effects while enabling continued functionality.
2Loss of energy
If dummy cells are added to reduce leakage, then power leakage is reduced, but device complexity increases
Solution Approach 1:
The patent applies dummy cells selectively only in non-critical paths where leakage would otherwise affect circuit operation. By targeting specific local regions rather than uniformly applying leakage reduction across the entire device, the solution reduces power leakage in critical areas while minimizing the addition of dummy cells in non-critical areas, thus balancing leakage reduction with complexity management.
Solution Approach 2:
The dummy cells are merged with the existing master-slave latch structure by sharing common transistors and circuit paths. The dummy cell transistors are integrated into the feedback paths of the latches, allowing the leakage reduction function to be combined with the existing data storage functionality without requiring completely separate circuitry, thereby reducing the net increase in device complexity.
Data Source
AI summary
The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.