Dummy Cell Layout for Planar High-Voltage IC Buffer Areas
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Solution Overview
Problem
In high-voltage integrated circuits, the absence of dummy elements in buffer areas leads to false endpoint detection during etching and chemical/mechanical polishing due to non-planar surfaces caused by LOCOS layers, resulting in dielectric breakdown and potential device failure.
Innovation Solution
The introduction of dummy cells with polysilicon structures positioned relative to LOCOS regions such that their perimeters never intersect, eliminating the bird's beak area and preventing dielectric breakdown by ensuring a planar surface for accurate endpoint detection and process uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dummy elements are not formed in buffer areas, then device complexity is reduced, but false endpoint detection occurs during etching and CMP processes
Solution Approach 1:
The patent creates dummy cells that replicate the structural characteristics of active device regions, including LOCOS regions with bird's beak features and epitaxial regions. These copied structures provide the necessary material removal characteristics for accurate endpoint detection without requiring full functional devices in buffer areas.
Solution Approach 2:
The dummy cells are designed with specific geometric parameters and material compositions that match the active regions. By controlling the size, shape, and material properties of the dummy structures, the patent optimizes their ability to provide accurate endpoint detection signals while minimizing their impact on device complexity.
2Reliability
If LOCOS regions with bird's beak are present in buffer areas, then isolation is achieved, but non-planar surfaces cause dielectric breakdown
Solution Approach 1:
The patent applies different structural characteristics to different locations within the dummy cell. The LOCOS regions are positioned and shaped to provide local isolation where needed, while the overall dummy cell structure maintains a planar top surface. This localized approach allows isolation functionality without compromising dielectric integrity.
Solution Approach 2:
The patent resolves the surface non-planarity issue by transitioning from a two-dimensional surface problem to a three-dimensional structural solution. The dummy cells incorporate vertical depth variations through LOCOS regions and epitaxial layers, but are configured so that the top surface remains planar, effectively adding a depth dimension while maintaining surface uniformity.
3Ease of manufacture
If polysilicon structure perimeter crosses LOCOS region perimeter, then manufacturing is simplified, but dielectric breakdown occurs at intersection points
Solution Approach 1:
The patent deliberately creates an asymmetric relationship between the polysilicon structure and LOCOS region perimeters. Rather than allowing symmetric overlap or crossing, the design ensures that the polysilicon perimeter is positioned to never intersect the LOCOS perimeter, creating a clear spatial separation that prevents dielectric breakdown at intersection points.
Solution Approach 2:
The patent takes preliminary action during the design stage to prevent dielectric breakdown by ensuring that the polysilicon and LOCOS perimeters never cross. This preventive design approach eliminates the harmful effect before it can occur during device operation, rather than attempting to mitigate it afterward.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances etch and CMP process uniformity, reduces dielectric breakdown risks, and maintains device integrity by maintaining a planar surface, thereby improving the reliability of high-voltage integrated circuits.
Implementation Method 1
a local oxidation of silicon (LOCOS) region having a bird's beak at a perimeter of the LOCOS region
Implementation Method 2
When etching or chemical/mechanical polishing, the material that is removed is monitored to help determine the etching endpoint
Implementation Method 3
When etching or chemical/mechanical polishing, the material that is removed is monitored to help determine the etching endpoint
Data Source
AI summary
Described examples include an integrated circuit having a substrate. The integrated circuit also has at least one dummy cell on the substrate, the dummy cell having at least a first component having an edge in a first layer of components on the substrate and at least a second component in a second layer of components, the second layer of components on the first layer of components and the substrate, wherein no part of the second component is proximate to the edge of the first component. The integrated circuit also has an insulating layer on the first layer of components and the second layer of components, the insulating layer having a first surface opposite to a second surface of the insulating layer on the first layer of components and the second layer of components, wherein the first surface is planarized and a patterned conductor layer on the first surface.