Dummy Cell Power Via Structure for Dense Semiconductor Layouts
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density and reliable power delivery networks while maintaining efficient voltage application to power lines, which limits their performance and functionality.
Innovation Solution
The semiconductor device incorporates a substrate with dummy regions, device isolation layers, and through vias that connect a power delivery network to expanded power lines, allowing for stable voltage application and reduced electrical influence on neighboring logic cells, thereby enhancing integration density and routing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased, then device functionality and performance are improved, but power delivery reliability and voltage stability deteriorate
Solution Approach 1:
The device is divided into logic cells and dummy cells that are spatially separated and independently configured. The dummy cells are positioned at regular intervals to provide localized power delivery support, while logic cells contain the functional circuitry. This segmentation allows power delivery functions to be distributed throughout the device, maintaining reliability while achieving high integration density in the logic regions.
Solution Approach 2:
Dummy cells act as intermediary structures between the substrate and logic cells, providing power delivery support without containing functional logic. These dummy cells include through vias and expanded portions that serve as mediators for voltage application, isolating the power delivery function from the logic cells while maintaining electrical connection to the substrate.
2Reliability
If power delivery network is expanded to cover larger areas, then voltage application stability is improved, but device area and integration density worsen
Solution Approach 1:
Instead of uniformly expanding the power delivery network across the entire device area, the patent applies power delivery structures selectively in dummy cells at specific locations. Each dummy cell contains through vias and expanded portions with locally optimized dimensions and spacing. This local quality approach provides stable voltage application where needed while minimizing the total area occupied by power delivery infrastructure.
3Reliability
If through vias are added to connect power delivery network to logic cells, then electrical connection reliability is improved, but manufacturing complexity and device area worsen
Solution Approach 1:
The patent merges the power delivery function with the cell structure by integrating through vias and expanded portions directly into the dummy cells. Rather than adding separate power delivery components, the dummy cells themselves are configured to provide electrical connection from the substrate to the power lines. This merging reduces manufacturing complexity by consolidating multiple functions into unified structures.
4Reliability
If dummy regions are introduced to support power delivery, then voltage delivery stability is improved, but logic cell area and integration density worsen
Solution Approach 1:
The patent transitions from two-dimensional planar power delivery to three-dimensional vertical power delivery by introducing through vias that extend from the substrate through the dummy cells to the power lines. The expanded portions provide vertical overlap with the through vias, creating a three-dimensional power delivery pathway. This dimensional change allows stable voltage delivery without increasing the planar area occupied by dummy regions.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.