Dummy Cell Feedback Path for Low-Leakage Scan Flip-Flops
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Solution Overview
Problem
In semiconductor devices, particularly in systems-on-chip (SoCs) using deep-micron technologies, it is challenging to reduce power leakage in sequential cells such as scannable D flip-flops and data latches due to increasing transistor counts.
Innovation Solution
The implementation of leakage-free dummy cells in non-critical paths of scannable D flip-flops and data latches, specifically using transistors with their gates connected to nodes and sources and drains grounded, reduces leakage current by acting as dummy cells within the master and slave feedback circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistor count is increased to meet system requirements, then device functionality is improved, but power leakage increases
Solution Approach 1:
A dummy cell is introduced as an intermediary element in the feedback path of the sequential circuit. This dummy cell acts as a mediator that provides a controlled leakage path, preventing leakage current from affecting the critical data storage nodes. The dummy cell includes a transistor with its gate connected to a control node and its drain connected to ground, creating a dedicated leakage pathway that isolates the main functional nodes from leakage effects.
Solution Approach 2:
The leakage problem is extracted and isolated from the critical functional paths by placing the dummy cell in a non-critical feedback path. By separating the leakage current into a dedicated dummy path, the harmful leakage effects are removed from the data storage nodes while maintaining the necessary transistor count for device functionality.
2Loss of energy
If dummy cells are added to reduce leakage, then power leakage is reduced, but device complexity increases
Solution Approach 1:
The dummy cell serves multiple functions simultaneously: it provides a leakage path for power reduction, maintains the feedback signal flow for circuit operation, and can be integrated into existing feedback paths without requiring separate dedicated structures. The same transistor structure that forms part of the feedback logic also serves as the leakage reduction mechanism, eliminating the need for completely separate leakage reduction circuitry.
3Loss of energy
If dummy cells are placed in feedback paths, then leakage current is reduced, but operating speed may be affected
Solution Approach 1:
The dummy cell is strategically placed in specific non-critical feedback paths where leakage reduction is most beneficial without impacting critical timing paths. By selectively applying leakage reduction only in appropriate locations rather than uniformly across all feedback paths, the circuit maintains high operating speed in critical paths while achieving leakage reduction in non-critical paths.
Data Source
AI summary
The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.