Dummy Channel Through-Wiring Layout for Pattern Uniformity
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Solution Overview
Problem
As demand for high performance, high speed, and multifunctionality in semiconductor devices increases, achieving uniform pattern formation across the entire semiconductor device becomes challenging due to the high integration density, leading to reliability issues.
Innovation Solution
The semiconductor device incorporates a through wiring region with dummy channel structures that partially extend into an insulating region, having a different height and pitch compared to the channel structures, to maintain pattern uniformity and reduce defects, while the through contact plugs electrically connect the memory cell region to the peripheral circuit region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integration density is increased to achieve high performance and multifunctionality, then device capability is improved, but pattern uniformity deteriorates leading to reliability issues
Solution Approach 1:
The patent introduces dummy channel structures specifically in the through wiring region adjacent to memory cell regions, while maintaining different pitch arrangements in different areas. This local modification approach addresses pattern uniformity issues in specific critical regions without changing the overall high-density architecture, thereby resolving the contradiction between high integration density and pattern uniformity.
Solution Approach 2:
The patent creates dummy channel structures that replicate the form and arrangement of actual channel structures in the memory cell region. These copied structures are placed in the through wiring region to provide pattern uniformity reference, allowing the manufacturing process to maintain consistent patterning quality across different regions despite the high integration density.
2Quantity of substance
If channel structures are formed with high density, then integration density is improved, but pattern formation uniformity across the entire device deteriorates
Solution Approach 1:
The patent applies different pitch arrangements locally: memory cell regions use a first pitch optimized for high integration density, while through wiring regions use a second pitch (different from the first) to ensure pattern formation uniformity. This local differentiation allows high density where needed while maintaining manufacturing precision in critical wiring areas.
Solution Approach 2:
The patent segments the device into distinct regions (memory cell regions and through wiring regions) with different channel structure pitch arrangements. This segmentation allows each region to be optimized independently - memory regions for high density and wiring regions for pattern uniformity - thereby resolving the contradiction between quantity and manufacturing precision.
3Manufacturing precision
If through wiring region is designed with different pitch than channel structures, then pattern uniformity is improved, but device complexity increases
Solution Approach 1:
The patent introduces pitch differentiation only in specific through wiring regions adjacent to memory cell regions, rather than throughout the entire device. This localized approach maintains pattern uniformity where it is most critical while minimizing the overall structural complexity and avoiding unnecessary modifications in other regions.
Data Source
AI summary
A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.