Dummy Chip Package Structure for Reliable Stacked Chip Bonding
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, large capacity, miniaturization, and reliability due to the limitations in stacking semiconductor chips and ensuring effective bonding and protection.
Innovation Solution
A semiconductor package design incorporating a dummy chip with specific adhesive layers and protrusion portions, along with a molding layer that covers the side surfaces, enhancing the bonding and protection of stacked semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked to achieve high performance and large capacity, then the functionality and storage capacity are improved, but the reliability and bonding strength between chips deteriorate
Solution Approach 1:
The adhesive layer is segmented into multiple functional zones: a first adhesive portion for bonding the lower chip, a second adhesive portion for bonding the upper chip, and protrusion portions extending laterally to provide mechanical interlocking. This segmentation allows each zone to perform its specific function optimally, improving overall bonding reliability in stacked chip configurations.
Solution Approach 2:
The adhesive layer transitions from a simple planar structure to a three-dimensional structure with protrusion portions extending in the lateral direction. This dimensional change provides additional bonding surfaces and mechanical interlocking features, enhancing bonding strength without increasing the vertical stack height, thus maintaining high density while improving reliability.
2Ease of manufacture
If the molding layer covers only the top surface, then the manufacturing process is simple, but the adhesive layer remains exposed and reliability is reduced
Solution Approach 1:
The molding layer is designed to extend laterally along the side surfaces of the chips and adhesive layer during the molding process itself, rather than requiring subsequent processing steps. This preliminary action of extending coverage during the primary molding operation achieves complete coverage without exposing the adhesive layer, maintaining both ease of manufacture and improved reliability through a single integrated process.
Data Source
AI summary
A semiconductor package includes a base structure, a lower semiconductor chip disposed on the base structure, an upper semiconductor chip disposed on the lower semiconductor chip, a connecting structure including a lower pad disposed on the lower semiconductor chip, an upper pad disposed under the upper semiconductor chip, and a connecting bump disposed between the lower pad and the upper pad, a dummy chip disposed on the upper semiconductor chip, an upper adhesive layer including an upper adhesive portion disposed between the upper semiconductor chip and the dummy chip, and an upper protrusion portion disposed at opposite sides of the upper adhesive portion, to surround lower portions of opposite side surfaces of the dummy chip, and a molding layer disposed at opposite sides of the dummy chip, to surround upper portions of the opposite side surfaces of the dummy chip and the upper protrusion portion.