Dummy Chip Interposer Layout for FOWLP Warpage Reduction
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Solution Overview
Problem
Wafer-level packaging faces challenges due to the complexity and cost of TSV interposers and warpage issues caused by thick molding compounds, which hinder the assembly of fine-pitch RDL processes and increase manufacturing costs.
Innovation Solution
A semiconductor device and method that reduces the amount of molding compound by using dummy chips mounted on a substrate-less interposer with a redistribution layer, where dummy chips are placed in the peripheral area to minimize warpage, and the interposer is fabricated without TSVs, using a carrier with adhesive layers and a redistribution layer formed with dielectric and metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick layer of molding compound is used to cover the wafer and dies, then the packaging is more robust and protective, but warpage increases due to CTE mismatch and the overall thickness increases
Solution Approach 1:
The patent extracts and removes the TSV interposer substrate from the packaging structure, eliminating the source of CTE mismatch that causes warpage. By using a carrier-less approach with direct die-to-die or die-to-wafer bonding, the thick molding compound layer is no longer needed for structural support, thereby reducing warpage while maintaining protective coverage.
Solution Approach 2:
The patent changes the physical and material parameters of the packaging structure by eliminating the interposer substrate and using thin-film polymers and metallization for redistribution. This parameter change reduces the overall thickness and CTE mismatch, thereby reducing warpage while maintaining the protective function of the molding compound.
2Ease of manufacture
If a TSV interposer substrate is used for FOWLP, then contact redistribution is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent extracts and eliminates the TSV interposer substrate from the FOWLP process. Instead of using a separate interposer layer with through-substrate vias, the invention uses direct die bonding to the carrier or to each other, with redistribution achieved through RDL layers formed directly on the dies or carrier, thereby simplifying the manufacturing process and reducing cost.
Solution Approach 2:
The patent makes the carrier serve multiple functions: it provides mechanical support, enables contact redistribution, and facilitates thermal management. By eliminating the need for a separate TSV interposer, the carrier becomes a multi-functional element that performs both structural and electrical redistribution functions, reducing overall device complexity.
3Ease of manufacture
If a TSV interposer substrate is used for FOWLP, then contact redistribution is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the TSV interposer substrate from the FOWLP process. Instead of using a separate interposer layer with through-substrate vias, the invention uses direct die bonding to the carrier or to each other, with redistribution achieved through RDL layers formed directly on the dies or carrier, thereby simplifying the manufacturing process and reducing cost.
Solution Approach 2:
The patent makes the carrier serve multiple functions: it provides mechanical support, enables contact redistribution, and facilitates thermal management. By eliminating the need for a separate TSV interposer, the carrier becomes a multi-functional element that performs both structural and electrical redistribution functions, reducing overall device complexity.
4Productivity
If large-sized wafers are used for wafer-level packaging, then production capacity increases, but warpage becomes more severe and prevents successful assembly
Solution Approach 1:
The patent extracts and removes the TSV interposer substrate that causes CTE mismatch and warpage. By using a carrier-less approach with direct die bonding, large-sized wafers can be processed without the severe warpage that would otherwise prevent successful assembly, thereby enabling high-volume production while maintaining assembly success rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces warpage and manufacturing costs by minimizing the use of molding compound and eliminating the need for TSV interposers, enabling more efficient assembly and production of wafer-level packages with improved thermal expansion matching.
Implementation Method 1
a carrier with adhesive layers
Implementation Method 2
a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one dummy chip
Implementation Method 3
a plurality of solder bumps mounted on the second side
Data Source
AI summary
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.