Scrambled Dummy Column Memory for Side-Channel Masking in IMC
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Solution Overview
Problem
In-memory computation (IMC) processing systems are vulnerable to side channel attacks that attempt to extract proprietary computational weight data, necessitating improved security measures.
Innovation Solution
The implementation of dummy columns with randomly precharged bit lines and modulated word line signals, combined with polarity control and column masking, enhances security by introducing random variations in power consumption patterns, making it difficult for attackers to discern stored data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational weight data is stored in the memory array for in-memory computation operations, then computation performance is improved, but vulnerability to side channel attacks increases
Solution Approach 1:
The patent introduces dummy columns as intermediary elements between the actual data storage and the external observation point (power consumption measurements). These dummy columns act as a mediator that absorbs and masks the power consumption signatures of the actual computational weight data, preventing attackers from directly observing and extracting sensitive information through side channel attacks while allowing the system to maintain its computational functionality
2Reliability
If dummy columns are added to the memory array, then security against side channel attacks is improved, but memory array complexity increases
Solution Approach 1:
The patent applies homogeneity by making the dummy columns structurally identical to the actual data columns in the memory array. Both dummy columns and real columns use the same memory cell structures, word lines, and bit lines. This structural uniformity allows the dummy columns to be seamlessly integrated into the existing memory architecture without requiring additional complex control logic or specialized components, thereby enhancing security while minimizing increases in device complexity
Data Source
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AI summary
A circuit memory includes sub-arrays with memory cells (storing weight data for an in-memory computation operation) arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. For in-memory computation operation execution, a control circuit simultaneously actuates one word line per sub-array. An input/output circuit for each column includes bit line inputs to the local bit lines of the sub-arrays and a sub-array data output coupled to each bit line input. Bit lines of the sub-arrays in a dummy column of the memory are precharged to a randomly selected one of first and second voltage levels in connection with execution of the in-memory computation operation to provide a randomization of circuit power consumption as a measure to protect the memory from a side channel attack to extract the weight data.