Dummy Dies Enable Extended HBM Offsets in 2.5D Interposers
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Solution Overview
Problem
In 2.5D interposers, high-bandwidth memory (HBM) devices often require offsets due to IC size mismatches, leading to routing challenges that cannot be resolved by increasing ASIC size, which is impractical and costly, especially when design rules restrict chip area expansion.
Innovation Solution
Inserting dummy dies between ASIC and HBM on the interposer to increase the escape region, allowing 45-degree or orthogonal routing at extended offsets without enlarging the ASIC, using metallic dummy dies that maintain die-to-die gap rules and ensure signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If HBM is offset from corresponding PHY circuit pins due to IC size mismatches, then routing flexibility is improved, but routing difficulty increases
Solution Approach 1:
The patent introduces dummy dies as intermediary elements between the HBM and the PHY circuit pins. These dummy dies serve as mediators that facilitate routing connections at extended offsets by providing additional escape regions and routing paths, thereby resolving the routing difficulty while maintaining the offset configuration for adaptability
2Ease of operation
If ASIC size is increased to resolve routing challenges, then routing capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the interposer structure by inserting dummy dies between the HBM and the PHY circuit. This segmentation creates additional escape regions and routing paths without requiring an increase in the ASIC die size, thereby maintaining manufacturing cost effectiveness while improving routing capability
3Area of stationary object
If chip area is expanded to accommodate routing, then routing space is improved, but design rule compliance becomes difficult
Solution Approach 1:
The patent utilizes the vertical dimension of the interposer by stacking dummy dies between the HBM and the PHY circuit pins. This approach increases the available escape region and routing space in the vertical direction rather than expanding the chip area horizontally, thereby maintaining design rule compliance while providing sufficient routing space
Data Source
AI summary
A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.


