Stacked Semiconductor Package with Dummy Electrodes for Higher Yield
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance, high capacity, and miniaturization while maintaining reliability, particularly in stacked semiconductor chips with through silicon vias.
Innovation Solution
A semiconductor package design incorporating a first semiconductor chip with pads and insulating layers, a second semiconductor chip with through electrodes, and a third semiconductor chip with dummy electrode structures, along with encapsulation and bump structures, to enhance signal transmission and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in a perpendicular direction to achieve miniaturization and high capacity, then device density and capacity are improved, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The patent divides the semiconductor device into multiple stacked chips (first, second, and third semiconductor chips) with distinct functional layers. Each chip contains specific components such as pads, insulating layers, through electrodes, and dummy electrode structures, allowing complex functionality to be achieved through modular stacking rather than monolithic integration.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically with encapsulants and connection structures nested between them. The second and third chips are positioned below the first chip, with encapsulants sealing the interfaces, creating a compact nested arrangement that maximizes space utilization.
2Reliability
If through electrodes are used to connect stacked chips, then electrical connectivity between layers is improved, but signal transmission paths and manufacturing difficulty increase
Solution Approach 1:
The patent introduces dummy electrode structures on the third semiconductor chip that replicate the function of through electrodes without requiring actual electrical connections. These dummy electrodes have the same width and configuration as through electrodes, simplifying manufacturing by allowing identical fabrication processes for both functional and dummy electrodes.
Solution Approach 2:
The patent applies different electrode configurations to different regions: through electrodes are used where electrical connectivity is needed (second chip), while dummy electrodes are used where only structural support is needed (third chip). This local differentiation optimizes both electrical performance and manufacturing simplicity.
3Productivity
If dummy electrode structures with greater width are used, then manufacturing is simplified and yield is improved, but device area increases
Solution Approach 1:
The patent uses dummy electrodes with widths equal to or greater than through electrodes, providing excess structural support beyond the minimum required for electrical connection. This excessive width simplifies manufacturing alignment and improves yield, while the dummy electrodes are positioned in regions where they do not interfere with active device areas.
Data Source
AI summary
A method of manufacturing a semiconductor package includes preparing a semiconductor wafer including a plurality of first semiconductor chips, wherein each of the plurality of first semiconductor chips includes first pads and a first insulating layer surrounding the first pads, disposing a second semiconductor chip and a third semiconductor chip on each of the plurality of first semiconductor chips, forming an encapsulant sealing at least a portion of each of the second and third semiconductor chips, wherein the encapsulant covers side surfaces of the second opposite pads, and forming bump structures on the second and third semiconductor chips, wherein the bump structures are electrically connected to the first opposite pads and the second opposite pads.